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Xeon D-1649N - Intel
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Xeon D-1649N | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | D-1649N |
Market | Server, Embedded |
Introduction | April 2, 2019 (announced) April 2, 2019 (launched) |
Release Price | $705.00 (tray) |
Shop | Amazon |
General Specs | |
Family | Xeon D |
Series | D-1600 |
Locked | Yes |
Frequency | 2,300 MHz |
Turbo Frequency | 2,500 MHz (1 core) |
Bus type | DMI 2.0 |
Clock multiplier | 23 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Broadwell |
Platform | Grangeville |
Core Name | Hewitt Lake |
Core Family | 6 |
Core Model | 6 |
Process | 14 nm |
Transistors | 3,200,000,000 |
Technology | CMOS |
Die | 246.24 mm² |
Word Size | 64 bit |
Cores | 8 |
Threads | 16 |
Max Memory | 128 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
TDP | 45 W |
Packaging | |
Package | FCBGA-1667 (FCBGA) |
Dimension | 37.5 mm × 37.5 mm × 3.557 mm |
Pitch | 0.7 mm |
Contacts | 1667 |
Xeon D-1649N is a 64-bit octa-core x86 microserver SoC introduced by Intel in early 2019. The D-1649N is based on the Broadwell microarchitecture and is fabricated on their 14 nm process. It operates at 2.3 GHz with a TDP of 45 W and a turbo frequency of 2.5 GHz. This processor supports up to 128 GiB of dual-channel DDR4-2400 memory.
Cache
- Main article: Broadwell § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Graphics
This SoC has no integrated graphics processing unit.
Memory controller
Integrated Memory Controller
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Expansions
Expansion Options |
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Networking
Networking
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Features
[Edit/Modify Supported Features]
Facts about "Xeon D-1649N - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon D-1649N - Intel#pcie + |
back image | + |
base frequency | 2,300 MHz (2.3 GHz, 2,300,000 kHz) + |
bus type | DMI 2.0 + |
clock multiplier | 23 + |
core count | 8 + |
core family | 6 + |
core model | 6 + |
core name | Hewitt Lake + |
designer | Intel + |
die area | 246.24 mm² (0.382 in², 2.462 cm², 246,240,000 µm²) + |
family | Xeon D + |
first announced | April 2, 2019 + |
first launched | April 2, 2019 + |
full page name | intel/xeon d/d-1649n + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Trusted Execution Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Secure Key Technology +, OS Guard + and Integrated QuickAssist Technology + |
has integrated intel quickassist technology | true + |
has intel enhanced speedstep technology | true + |
has intel secure key technology | true + |
has intel supervisor mode execution protection | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) + |
ldate | April 2, 2019 + |
main image | + |
manufacturer | Intel + |
market segment | Server + and Embedded + |
max cpu count | 1 + |
max memory | 131,072 MiB (134,217,728 KiB, 137,438,953,472 B, 128 GiB, 0.125 TiB) + |
max memory bandwidth | 31.78 GiB/s (32,542.72 MiB/s, 34.124 GB/s, 34,123.515 MB/s, 0.031 TiB/s, 0.0341 TB/s) + |
max memory channels | 2 + |
max sata ports | 6 + |
max usb ports | 4 + |
microarchitecture | Broadwell + |
model number | D-1649N + |
name | Xeon D-1649N + |
package | FCBGA-1667 + |
platform | Grangeville + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 705.00 (€ 634.50, £ 571.05, ¥ 72,847.65) + |
release price (tray) | $ 705.00 (€ 634.50, £ 571.05, ¥ 72,847.65) + |
series | D-1600 + |
smp max ways | 1 + |
supported memory type | DDR4-2133 + |
tdp | 45 W (45,000 mW, 0.0603 hp, 0.045 kW) + |
technology | CMOS + |
thread count | 16 + |
transistor count | 3,200,000,000 + |
turbo frequency (1 core) | 2,500 MHz (2.5 GHz, 2,500,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |