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EPYC 7371 - AMD
Edit Values | |
EPYC 7371 | |
General Info | |
Designer | AMD |
Manufacturer | GlobalFoundries |
Model Number | 7371 |
Market | Server |
Introduction | November 13, 2018 (announced) 2019 (launched) |
Shop | Amazon |
General Specs | |
Family | EPYC |
Series | 7000 |
Locked | No |
Frequency | 3,100 MHz |
Turbo Frequency | 3,800 MHz (1 core), 3,800 MHz (2 cores), 3,800 MHz (3 cores), 3,800 MHz (4 cores), 3,800 MHz (5 cores), 3,800 MHz (6 cores), 3,800 MHz (7 cores), 3,800 MHz (8 cores), 3,600 MHz (9 cores), 3,600 MHz (10 cores), 3,600 MHz (11 cores), 3,600 MHz (12 cores), 3,600 MHz (13 cores), 3,600 MHz (14 cores), 3,600 MHz (15 cores), 3,600 MHz (16 cores) |
Clock multiplier | 31 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Zen |
Core Name | Naples |
Core Family | 23 |
Core Model | 1 |
Core Stepping | B2 |
Process | 14 nm |
Transistors | 19,200,000,000 |
Technology | CMOS |
Die | 213 mm² |
MCP | Yes (4 dies) |
Word Size | 64 bit |
Cores | 16 |
Threads | 32 |
Max Memory | 2 TiB |
Multiprocessing | |
Max SMP | 2-Way (Multiprocessor) |
Packaging | |
Template:packages/amd/socket sp3 |
EPYC 7371 is a dual-socket 64-bit 16-core x86 enterprise server microprocessor introduced by AMD in late 2018. This processor is based on the Zen microarchitecture and is manufactured on a 14 nm process. The 7371 has a base frequency of 3.1 GHz with a turbo frequency of up to 3.8 GHz. This chip has a TDP of ? W and supports up to 2 TiB of octa-channel DDR4-2666 ECC memory per socket.
Contents
Cache
- Main article: Zen § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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In a dual-socket configuration, the maximum supported memory doubles to 4 TiB along with the maximum theoretical bandwidth of 317.9 GiB/s.
Expansions
The EPYC 7351P has 128 Gen 3 PCIe lanes.
Expansion Options
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Features
[Edit/Modify Supported Features]
Facts about "EPYC 7371 - AMD"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | EPYC 7371 - AMD#io + |
base frequency | 3,100 MHz (3.1 GHz, 3,100,000 kHz) + |
clock multiplier | 31 + |
core count | 16 + |
core family | 23 + |
core model | 1 + |
core name | Naples + |
core stepping | B2 + |
designer | AMD + |
die area | 213 mm² (0.33 in², 2.13 cm², 213,000,000 µm²) + |
die count | 4 + |
family | EPYC + |
first announced | November 13, 2018 + |
first launched | 2019 + |
full page name | amd/epyc/7371 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has amd amd-v technology | true + |
has amd amd-vi technology | true + |
has amd secure encrypted virtualization technology | true + |
has amd secure memory encryption technology | true + |
has amd sensemi technology | true + |
has amd transparent secure memory encryption technology | true + |
has ecc memory support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension + and SenseMI Technology + |
has locked clock multiplier | false + |
has simultaneous multithreading | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
is multi-chip package | true + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 1,536 KiB (1,572,864 B, 1.5 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1i$ description | 4-way set associative + |
l1i$ size | 1,024 KiB (1,048,576 B, 1 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 64 MiB (65,536 KiB, 67,108,864 B, 0.0625 GiB) + |
ldate | 2019 + |
manufacturer | GlobalFoundries + |
market segment | Server + |
max cpu count | 2 + |
max memory | 2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) + |
max memory bandwidth | 158.95 GiB/s (162,764.8 MiB/s, 170.671 GB/s, 170,671.263 MB/s, 0.155 TiB/s, 0.171 TB/s) + |
max memory channels | 8 + |
max pcie lanes | 128 + |
microarchitecture | Zen + |
model number | 7371 + |
name | EPYC 7371 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
series | 7000 + |
smp max ways | 2 + |
supported memory type | DDR4-2666 + and DDR4-2400 + |
technology | CMOS + |
thread count | 32 + |
transistor count | 19,200,000,000 + |
turbo frequency (10 cores) | 3,600 MHz (3.6 GHz, 3,600,000 kHz) + |
turbo frequency (11 cores) | 3,600 MHz (3.6 GHz, 3,600,000 kHz) + |
turbo frequency (12 cores) | 3,600 MHz (3.6 GHz, 3,600,000 kHz) + |
turbo frequency (13 cores) | 3,600 MHz (3.6 GHz, 3,600,000 kHz) + |
turbo frequency (14 cores) | 3,600 MHz (3.6 GHz, 3,600,000 kHz) + |
turbo frequency (15 cores) | 3,600 MHz (3.6 GHz, 3,600,000 kHz) + |
turbo frequency (16 cores) | 3,600 MHz (3.6 GHz, 3,600,000 kHz) + |
turbo frequency (1 core) | 3,800 MHz (3.8 GHz, 3,800,000 kHz) + |
turbo frequency (2 cores) | 3,800 MHz (3.8 GHz, 3,800,000 kHz) + |
turbo frequency (3 cores) | 3,800 MHz (3.8 GHz, 3,800,000 kHz) + |
turbo frequency (4 cores) | 3,800 MHz (3.8 GHz, 3,800,000 kHz) + |
turbo frequency (5 cores) | 3,800 MHz (3.8 GHz, 3,800,000 kHz) + |
turbo frequency (6 cores) | 3,800 MHz (3.8 GHz, 3,800,000 kHz) + |
turbo frequency (7 cores) | 3,800 MHz (3.8 GHz, 3,800,000 kHz) + |
turbo frequency (8 cores) | 3,800 MHz (3.8 GHz, 3,800,000 kHz) + |
turbo frequency (9 cores) | 3,600 MHz (3.6 GHz, 3,600,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |