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From WikiChip
Carmel - Microarchitectures - Nvidia
< nvidia
| Edit Values | |
| Carmel µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Nvidia |
| Manufacturer | TSMC |
| Introduction | January 7, 2018 |
| Process | 12 nm |
| Core Configs | 8 |
| Pipeline | |
| Type | Superscalar |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Stages | 10 |
| Instructions | |
| ISA | ARMv8 |
| Cache | |
| L2 Cache | 2 MiB/cluster |
| L3 Cache | 4 MiB/complex |
| Succession | |
Retrieved from "https://en.wikichip.org/w/index.php?title=nvidia/microarchitectures/carmel&oldid=81995"
Facts about "Carmel - Microarchitectures - Nvidia"
| codename | Carmel + |
| core count | 8 + |
| designer | Nvidia + |
| first launched | January 7, 2018 + |
| full page name | nvidia/microarchitectures/carmel + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv8 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Carmel + |
| pipeline stages | 10 + |
| process | 12 nm (0.012 μm, 1.2e-5 mm) + |