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From WikiChip
Cache Coherent Interconnect for Accelerators (CCIX)
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Cache Coherent Interconnect for Accelerators (CCIX), pronounced "see-six", is an open cache coherent interconnect architecture developed by the CCIX Consortium.
Overview
CCIX is a high-performance, low latency, chip-to-chip interconnect architecture that provides a cache coherent framework for heterogeneous system architectures. Cache coherency is automatically maintained at all time between the central processing unit and the various other accelerators in the system. CCIX supports signaling rates between 16 GT/s and 25 GT/s per link with support for link aggregation for higher performance.
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