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Ryzen Threadripper 2950X - AMD
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Ryzen Threadripper 2950X
General Info
DesignerAMD
ManufacturerGlobalFoundries
Model Number2950X
MarketDesktop
IntroductionAugust, 2018 (announced)
August, 2018 (launched)
ShopAmazon
General Specs
FamilyRyzen Threadripper
SeriesRyzen
LockedNo
Frequency3,500 MHz
Turbo Frequency4,400 MHz (1 core)
Bus rate4 × 8 GT/s
Clock multiplier35
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureZen+
Core Family23
Process12 nm
TechnologyCMOS
Die213 mm²
MCPYes (2 dies)
Word Size64 bit
Cores16
Threads32
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP180 W

Ryzen Threadripper 2950X is a 64-bit hexadeca-core high-performance x86 desktop microprocessor introduced by AMD in mid-2018. The 2950X, which is based on their Zen+ microarchitecture, is fabricated on a 12 nm process. The 2950X operates at a base frequency of 3.5 GHz with a TDP of 180 W and a boost of up to 4.4 GHz


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.


Water drop.svg Leaked Info! Some of the information presented in this article is solely based on leaks that were published online or obtained directly by WikiChip. It goes without saying that this information could change, be incomplete, wrong, or even made up. It's highly advised to wait for an official product announcement.


Cache

Main article: Zen+ § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1.5 MiB
1,536 KiB
1,572,864 B
L1I$1 MiB
1,024 KiB
1,048,576 B
16x64 KiB4-way set associative 
L1D$512 KiB
524,288 B
0.5 MiB
16x32 KiB8-way set associativewrite-back
L2$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  16x512 KiB8-way set associativewrite-back
L3$32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
  4x8 MiB16-way set associative 
Retrieved from "https://en.wikichip.org/w/index.php?title=amd/ryzen_threadripper/2950x&oldid=81003"
Facts about "Ryzen Threadripper 2950X - AMD"
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base frequency3,500 MHz (3.5 GHz, 3,500,000 kHz) +
bus links4 +
bus rate8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
clock multiplier35 +
core count16 +
core family23 +
designerAMD +
die area213 mm² (0.33 in², 2.13 cm², 213,000,000 µm²) +
die count2 +
familyRyzen Threadripper +
first announcedAugust 2018 +
first launchedAugust 2018 +
full page nameamd/ryzen threadripper/2950x +
has locked clock multiplierfalse +
instance ofmicroprocessor +
is multi-chip packagetrue +
isax86-64 +
isa familyx86 +
l1$ size1,536 KiB (1,572,864 B, 1.5 MiB) +
l1d$ description8-way set associative +
l1d$ size512 KiB (524,288 B, 0.5 MiB) +
l1i$ description4-way set associative +
l1i$ size1,024 KiB (1,048,576 B, 1 MiB) +
l2$ description8-way set associative +
l2$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
l3$ description16-way set associative +
l3$ size32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) +
ldate3000 +
manufacturerGlobalFoundries +
market segmentDesktop +
max cpu count1 +
microarchitectureZen+ +
model number2950X +
nameRyzen Threadripper 2950X +
process12 nm (0.012 μm, 1.2e-5 mm) +
seriesRyzen +
smp max ways1 +
tdp180 W (180,000 mW, 0.241 hp, 0.18 kW) +
technologyCMOS +
thread count32 +
turbo frequency (1 core)4,400 MHz (4.4 GHz, 4,400,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +