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Hi1612
General Info
Designer	HiSilicon, ARM Holdings
Manufacturer	TSMC
Model Number	Hi1610
Market	Server
Introduction	June 4, 2016 (announced) June 4, 2016 (launched)
General Specs
Family	Hi16xx
Frequency	2,100 MHz
Microarchitecture
ISA	ARMv8 (ARM)
Microarchitecture	Cortex-A57
Core Name	Cortex-A57
Technology	CMOS
Word Size	64 bit
Cores	32
Threads	32
Multiprocessing
Max SMP	1-Way (Uniprocessor)

Hi1612 is a dotriaconta-core 64-bit ARM server microprocessor introduced by HiSilicon in mid-2016. Fabricated by TSMC on a 16 nm process, this chip incorporates 32 Cortex-A57 cores operating at 2.1 GHz. The 1612 supports up to 256 GiB of DDR4-2133 memory.

Cache

Main article: Cortex-A57 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 2.5 MiB 2,560 KiB 2,621,440 B L1I$ 1.5 MiB 1,536 KiB 1,572,864 B 32x48 KiB 8-way set associative   L1D$ 1 KiB 1,024 B 9.765625e-4 MiB 32x32 KiB 8-way set associative   L2$ 8 MiB 8,192 KiB 8,388,608 B 0.00781 GiB     32x256 KiB 8-way set associative   L3$ 32 MiB 32,768 KiB 33,554,432 B 0.0313 GiB     32x1 MiB 16-way set associative