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Hi1612 - HiSilicon
Edit Values | |
Hi1612 | |
General Info | |
Designer | HiSilicon, ARM Holdings |
Manufacturer | TSMC |
Model Number | Hi1610 |
Market | Server |
Introduction | June 4, 2016 (announced) June 4, 2016 (launched) |
General Specs | |
Family | Hi16xx |
Frequency | 2,100 MHz |
Microarchitecture | |
ISA | ARMv8 (ARM) |
Microarchitecture | Cortex-A57 |
Core Name | Cortex-A57 |
Technology | CMOS |
Word Size | 64 bit |
Cores | 32 |
Threads | 32 |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Cache
- Main article: Cortex-A57 § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Facts about "Hi1612 - HiSilicon"
base frequency | 2,100 MHz (2.1 GHz, 2,100,000 kHz) + |
core count | 32 + |
core name | Cortex-A57 + |
designer | HiSilicon + and ARM Holdings + |
family | Hi16xx + |
first announced | June 4, 2016 + |
first launched | June 4, 2016 + |
full page name | hisilicon/kunpeng/hi1612 + |
instance of | microprocessor + |
isa | ARMv8 + |
isa family | ARM + |
l1$ size | 2,560 KiB (2,621,440 B, 2.5 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 1 KiB (1,024 B, 9.765625e-4 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 1,536 KiB (1,572,864 B, 1.5 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) + |
ldate | June 4, 2016 + |
manufacturer | TSMC + |
market segment | Server + |
max cpu count | 1 + |
microarchitecture | Cortex-A57 + |
model number | Hi1610 + |
name | Hi1612 + |
smp max ways | 1 + |
technology | CMOS + |
thread count | 32 + |
word size | 64 bit (8 octets, 16 nibbles) + |