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    Core M3-8114Y  - Intel    
                	
														| Edit Values | |
| M3-8114Y | |
| General Info | |
| Designer | Intel | 
| Manufacturer | Intel | 
| Model Number | M3-8114Y | 
| Market | Mobile | 
| Shop | Amazon | 
| General Specs | |
| Family | Core M3 | 
| Series | M3-8000 | 
| Locked | Yes | 
| Frequency | 1,500 MHz | 
| Turbo Frequency | 2,600 MHz (1 core) | 
| Bus type | OPI | 
| Bus rate | 4 GT/s | 
| Clock multiplier | 15 | 
| Microarchitecture | |
| ISA | x86-64 (x86) | 
| Microarchitecture | Cannon Lake | 
| Chipset | Cannon Point | 
| Core Name | Cannon Lake Y | 
| Core Family | 6 | 
| Core Model | 102 | 
| Process | 10 nm | 
| Technology | CMOS | 
| Word Size | 64 bit | 
| Cores | 2 | 
| Threads | 4 | 
| Max Memory | 16 GiB | 
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) | 
| Electrical | |
| TDP | 4.5 W | 
Core M3-8114Y is a 64-bit dual-core low-end performance ultra-low power x86 mobile microprocessor introduced by Intel in early 2018. This chip, which is based on the Cannon Lake microarchitecture, is fabricated on Intel's 10 nm process. The M3-8114Y operates at 1.5 GHz with a TDP of 4.5 W supporting a Turbo Boost frequency of 2.6 GHz. The processor supports up to 16 GiB of dual-channel LPDDR4X-2133 memory and incorporates Intel's HD Graphics 7?? IGP operating at ? MHz with a burst frequency of ? MHz.
Cache
- Main article: Cannon Lake § Cache
 
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 Cache Organization  
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.  | 
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Memory controller
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 Integrated Memory Controller 
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Expansions
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 Expansion Options 
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Graphics
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 Integrated Graphics Information 
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Features
[Edit/Modify Supported Features]
Facts about "Core M3-8114Y  - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.  | Core M3-8114Y - Intel#io + | 
| base frequency | 1,500 MHz (1.5 GHz, 1,500,000 kHz) + | 
| bus rate | 4,000 MT/s (4 GT/s, 4,000,000 kT/s) + | 
| bus type | OPI + | 
| chipset | Cannon Point + | 
| clock multiplier | 15 + | 
| core count | 2 + | 
| core family | 6 + | 
| core model | 102 + | 
| core name | Cannon Lake Y + | 
| designer | Intel + | 
| family | Core M3 + | 
| full page name | intel/core m/m3-8114y + | 
| has advanced vector extensions | true + | 
| has advanced vector extensions 2 | true + | 
| has ecc memory support | false + | 
| has extended page tables support | true + | 
| has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Memory Protection Extensions +, Software Guard Extensions +, Secure Key Technology +, OS Guard +, Flex Memory Access +, Smart Response Technology + and My WiFi Technology + | 
| has intel enhanced speedstep technology | true + | 
| has intel flex memory access support | true + | 
| has intel my wifi technology support | true + | 
| has intel secure key technology | true + | 
| has intel smart response technology support | true + | 
| has intel speed shift technology | true + | 
| has intel supervisor mode execution protection | true + | 
| has intel turbo boost technology 2 0 | true + | 
| has intel vt-d technology | true + | 
| has intel vt-x technology | true + | 
| has locked clock multiplier | true + | 
| has second level address translation support | true + | 
| has simultaneous multithreading | true + | 
| has x86 advanced encryption standard instruction set extension | true + | 
| instance of | microprocessor + | 
| integrated gpu | HD Graphics 7?? + | 
| integrated gpu designer | Intel + | 
| integrated gpu max memory | 16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB) + | 
| isa | x86-64 + | 
| isa family | x86 + | 
| l1$ size | 128 KiB (131,072 B, 0.125 MiB) + | 
| l1d$ description | 8-way set associative + | 
| l1d$ size | 64 KiB (65,536 B, 0.0625 MiB) + | 
| l1i$ description | 8-way set associative + | 
| l1i$ size | 64 KiB (65,536 B, 0.0625 MiB) + | 
| l2$ description | 4-way set associative + | 
| l2$ size | 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + | 
| l3$ description | 16-way set associative + | 
| l3$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + | 
| ldate | 3000 + | 
| manufacturer | Intel + | 
| market segment | Mobile + | 
| max cpu count | 1 + | 
| max memory | 16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB, 0.0156 TiB) + | 
| max memory bandwidth | 31.78 GiB/s (32,542.72 MiB/s, 34.124 GB/s, 34,123.515 MB/s, 0.031 TiB/s, 0.0341 TB/s) + | 
| max memory channels | 2 + | 
| max pcie lanes | 10 + | 
| microarchitecture | Cannon Lake + | 
| model number | M3-8114Y + | 
| name | M3-8114Y + | 
| process | 10 nm (0.01 μm, 1.0e-5 mm) + | 
| series | M3-8000 + | 
| smp max ways | 1 + | 
| supported memory type | LPDDR4-2133 + and LPDDR4X-2133 + | 
| tdp | 4.5 W (4,500 mW, 0.00603 hp, 0.0045 kW) + | 
| technology | CMOS + | 
| thread count | 4 + | 
| turbo frequency (1 core) | 2,600 MHz (2.6 GHz, 2,600,000 kHz) + | 
| word size | 64 bit (8 octets, 16 nibbles) + | 
| x86/has memory protection extensions | true + | 
| x86/has software guard extensions | true + |