Semiconductor & Computer Engineering
-
WikiChip
WikiChip
-
Architectures
Popular x86
-
Intel
- Client
- Server
- Big Cores
- Small Cores
-
AMD
Popular ARM
-
ARM
- Server
- Big
- Little
-
Cavium
-
Samsung
-
-
Chips
Popular Families
-
Ampere
-
Apple
-
Cavium
-
HiSilicon
-
MediaTek
-
NXP
-
Qualcomm
-
Renesas
-
Samsung
-
From WikiChip
Lake Crest - Microarchitectures - Intel Nervana
< nervana
| Edit Values | |
| Lake Crest µarch | |
| General Info | |
| Arch Type | NPU |
| Designer | Nervana |
| Manufacturer | TSMC |
| Introduction | November 17, 2016 |
| Process | 28 nm |
| Succession | |
Lake Crest is a neural processor microarchitecture designed by Nervana.
Process Technology
Lake Crest is fabricated on TSMC's 28 nm process.
Architecture
Lake Crest was designed from the ground up for deep learning
- Tensor-based architecture
- Nervana Engine
- Flexpoint number format
- HBM2 memory
- 32 GiB of in-package memory
- 8 Tbit/s bandwidth
- 12 bi-directional high-bandwidth direct chip-to-chip interconnect
This list is incomplete; you can help by expanding it.
Block Diagram
 |
This section is empty; you can help add the missing info by editing this page. |
Memory Hierarchy
- 32 GiB on-package HBM2
- 1 TiB/s
Retrieved from "https://en.wikichip.org/w/index.php?title=nervana/microarchitectures/lake_crest&oldid=76752"
Hidden category:
Facts about "Lake Crest - Microarchitectures - Intel Nervana"
| codename | Lake Crest + |
| designer | Nervana + |
| first launched | November 17, 2016 + |
| full page name | nervana/microarchitectures/lake crest + |
| instance of | microarchitecture + |
| manufacturer | TSMC + |
| name | Lake Crest + |
| process | 28 nm (0.028 μm, 2.8e-5 mm) + |