Semiconductor & Computer Engineering
From WikiChip
SHAVE v2.0 - Microarchitectures - Intel Movidius
| Edit Values | |
| SHAVE v2.0 µarch | |
| General Info | |
| Arch Type | Accelerator |
| Designer | Movidius |
| Manufacturer | TSMC |
| Introduction | 2011 |
| Pipeline | |
| Type | VLIW |
Streaming Hybrid Architecture Vector Engine v2.0 (SHAVE v2.0) is an accelerator microarchitecture designed by Movidius for their vision processors. SHAVE is incorporated into Movidius Myriad family of vision processors.
Contents
Architecture
- Hybrid RISC-DSP-GPU VLIW architecture
- Predicated execution
- Branch delay slots
- Tailored to streaming workloads
- 128-bit vector arithmetic
- 8/16/32-bit integer
- 16/32-bit floating point
- Full support for sparse data structures (matrix/array, random access)
Instruction Set
SHAVE supports a mixture of many different types of instructions belonging to a number of different classes of architectures.
- RISC style
- Instruction predication
- Large set of integer operations
- C-compiler support
- VLIW style
- Parallel functional units controlled by VLIW instructions
- 8/16/32-bit x 1-4 SIMD int
- DSP style
- Zero overhead looping
- Modulo addressing
- Transparent DMA modes
- FFT, Viterbi, etc..
- Parallel comparisons
- GPU style
- Streaming operations
- 16/32-bit FP operations
- Texture management unit
Block Diagram
Entire SoC
Individual Core
Facts about "SHAVE v2.0 - Microarchitectures - Intel Movidius"
| codename | SHAVE v2.0 + |
| designer | Movidius + |
| first launched | 2011 + |
| full page name | movidius/microarchitectures/shave v2.0 + |
| instance of | microarchitecture + |
| manufacturer | TSMC + |
| name | SHAVE v2.0 + |