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EPYC Embedded 3351 - AMD
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EPYC Embedded 3351
General Info
DesignerAMD
ManufacturerGlobalFoundries
Model Number3351
MarketServer, Embedded
IntroductionFebruary 21, 2018 (announced)
February 21, 2018 (launched)
ShopAmazon
General Specs
FamilyEPYC Embedded
Series3000
Frequency1,900 MHz
Turbo Frequency3,000 MHz (1 core)
Clock multiplier19
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureZen
Core NameSnowy Owl
Process14 nm
Transistors9,600,000,000
TechnologyCMOS
Die213 mm²
MCPYes (2 dies)
Word Size64 bit
Cores12
Threads24
Max Memory1 TiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP80 W
Tjunction0 °C – 95 °C
Packaging
Template:packages/amd/package sp4

EPYC Embedded 3351 is a 64-bit dodeca-core x86 embedded microprocessor introduced by AMD in early 2018 for dense servers and edge devices. Fabricated on a 14 nm process based on the Zen microarchitecture, this chip operates at 1.9 GHz with a TDP of 80 W and a turbo frequency of up to 3 GHz. The 3351 supports up to 1 TiB of quad-channel DDR4-2666 ECC memory.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.


Cache

Main article: Zen § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1.125 MiB
1,152 KiB
1,179,648 B
L1I$768 KiB
786,432 B
0.75 MiB
12x64 KiB4-way set associative 
L1D$384 KiB
393,216 B
0.375 MiB
12x32 KiB8-way set associativewrite-back
L2$6 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
  12x512 KiB8-way set associativewrite-back
L3$32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
  4x8 MiB16-way set associativewrite-back
Retrieved from "https://en.wikichip.org/w/index.php?title=amd/epyc_embedded/3351&oldid=74314"
Facts about "EPYC Embedded 3351 - AMD"
RDF feed
base frequency1,900 MHz (1.9 GHz, 1,900,000 kHz) +
clock multiplier19 +
core count12 +
core nameSnowy Owl +
designerAMD +
die area213 mm² (0.33 in², 2.13 cm², 213,000,000 µm²) +
die count2 +
familyEPYC Embedded +
first announcedFebruary 21, 2018 +
first launchedFebruary 21, 2018 +
full page nameamd/epyc embedded/3351 +
instance ofmicroprocessor +
is multi-chip packagetrue +
isax86-64 +
isa familyx86 +
l1$ size1,152 KiB (1,179,648 B, 1.125 MiB) +
l1d$ description8-way set associative +
l1d$ size384 KiB (393,216 B, 0.375 MiB) +
l1i$ description4-way set associative +
l1i$ size768 KiB (786,432 B, 0.75 MiB) +
l2$ description8-way set associative +
l2$ size6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) +
l3$ description16-way set associative +
l3$ size32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) +
ldateFebruary 21, 2018 +
manufacturerGlobalFoundries +
market segmentServer + and Embedded +
max cpu count1 +
max junction temperature368.15 K (95 °C, 203 °F, 662.67 °R) +
max memory1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) +
microarchitectureZen +
min junction temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
model number3351 +
nameEPYC Embedded 3351 +
process14 nm (0.014 μm, 1.4e-5 mm) +
series3000 +
smp max ways1 +
tdp80 W (80,000 mW, 0.107 hp, 0.08 kW) +
technologyCMOS +
thread count24 +
transistor count9,600,000,000 +
turbo frequency (1 core)3,000 MHz (3 GHz, 3,000,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +