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Xeon D-2183IT
General Info
Designer	Intel
Manufacturer	Intel
Model Number	D-2183IT
Part Number	FH8067303782501
S-Spec	SR3ZQ
Market	Server, Embedded
Introduction	February 7, 2018 (announced) February 7, 2018 (launched)
Release Price	$1764.00
Shop	Amazon
General Specs
Family	Xeon D
Series	D-2000
Locked	Yes
Frequency	2,200 MHz
Turbo Frequency	3,000 MHz (1 core)
Bus type	DMI 3.0
Bus rate	4 × 8 GT/s
Clock multiplier	22
Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Skylake (server)
Core Name	Skylake DE
Core Stepping	M1
Process	14 nm
Technology	CMOS
MCP	Yes (2 dies)
Word Size	64 bit
Cores	16
Threads	32
Max Memory	512 GiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
TDP	100 W
Packaging
Package FCBGA-2518 (BGA) Dimension 45 mm x 52.5 mm Contacts 2518

Xeon D-2183IT is a 64-bit 16-core high-performance x86 server microprocessor introduced by Intel in early 2018 for the dense server and edge computing market segment. Fabricated on Intel's 14 nm process based on the Skylake microarchitecture, this model operates at 2.2 GHz with a Turbo Boost of up to 3.0 GHz and a TDP of 100 W. The D-2183IT supports up to 512 GiB of quad-chanel DDR4-2400 ECC memory. This model is part of Skylake DE's Network Edge and Storage SKUs.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 1 MiB 1,024 KiB 1,048,576 B L1I$ 512 KiB 524,288 B 0.5 MiB 16x32 KiB 8-way set associative   L1D$ 512 KiB 524,288 B 0.5 MiB 16x32 KiB 8-way set associative write-back L2$ 16 MiB 16,384 KiB 16,777,216 B 0.0156 GiB     16x1 MiB 16-way set associative write-back L3$ 22 MiB 22,528 KiB 23,068,672 B 0.0215 GiB     16x1.375 MiB 11-way set associative write-back

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR4-2400 Supports ECC Yes Max Mem 512 GiB Controllers 2 Channels 4 Max Bandwidth 71.53 GiB/s 73,246.72 MiB/s 76.805 GB/s 76,804.753 MB/s 0.0699 TiB/s 0.0768 TB/s Bandwidth Single 17.88 GiB/s Double 35.76 GiB/s Quad 71.53 GiB/s Physical Address (PAE) 46 bit

Expansions

This chip incorporates 20 high-speed I/O (HSIO) lanes that may be configured as up to 20 PCIe lanes, up to 14 SATA 3.0 ports, or up to 4 USB 3.0 ports.

[Edit/Modify Expansions Info]

	Expansion Options
PCIe Revision: 3.0 Max Lanes: 32 Configuration: x16, x8, x4 HSIO Max Lanes: 20

Networking

[Edit/Modify Network Info]

	Networking
	Ethernet 10GbE Yes (Ports: 4)

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX MMX Extension EMMX Extended MMX Extension SSE Streaming SIMD Extensions SSE2 Streaming SIMD Extensions 2 SSE3 Streaming SIMD Extensions 3 SSSE3 Supplemental SSE3 SSE4.1 Streaming SIMD Extensions 4.1 SSE4.2 Streaming SIMD Extensions 4.2 AVX Advanced Vector Extensions AVX2 Advanced Vector Extensions 2 AVX-512 Advanced Vector 512-bit (1 Unit) AVX512F AVX-512 Foundation AVX512CD AVX-512 Conflict Detection AVX512BW AVX-512 Byte and Word AVX512DQ AVX-512 Doubleword and Quadword Instructions AVX512VL AVX-512 Vector Length ABM Advanced Bit Manipulation BMI1 Bit Manipulation Instruction Set 1 BMI2 Bit Manipulation Instruction Set 2 FMA3 3-Operand Fused-Multiply-Add AES AES Encryption Instructions RdRand Hardware RNG ADX Multi-Precision Add-Carry CLMUL Carry-less Multiplication Extension F16C 16-bit Floating Point Conversion x86-16 16-bit x86 x86-32 32-bit x86 x86-64 64-bit x86 Real Real Mode Protected Protected Mode SMM System Management Mode FPU Integrated x87 FPU NX No-eXecute HT Hyper-Threading TBT 2.0 Turbo Boost Technology 2.0 EIST Enhanced SpeedStep Technology SST Speed Shift Technology TXT Trusted Execution Technology (SMX) vPro Intel vPro VT-x VT-x (Virtualization) VT-d VT-d (I/O MMU virtualization) EPT Extended Page Tables (SLAT) TSX Transactional Synchronization Extensions MPX Memory Protection Extensions Secure Key Secure Key Technology SMEP OS Guard Technology VMD Volume Management Device IPT Identity Protection Technology

Frequencies

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

Mode	Base	Turbo Frequency/Active Cores