Edit Values |
R-Car M1S |
|
Designer | Renesas |
Manufacturer | TSMC |
Model Number | M1S |
Part Number | R8A77780 |
Market | Embedded |
Introduction | February 16, 2011 (announced) June, 2012 (launched) |
Release Price | $65 |
|
Family | R-Car |
Series | 1st Gen |
Frequency | 800 MHz |
|
ISA | SuperH (SuperH) |
Microarchitecture | SH-4A |
Core Name | SH-4A |
Process | 40 nm |
Technology | CMOS |
Word Size | 32 bit |
Cores | 1 |
Threads | 1 |
Max Memory | 1 GiB |
|
Vcore | 1.2 V |
VI/O | 3.3 V |
|
Package | FCBGA-472 (BGA) |
Dimension | 21 mm x 21 mm |
Pitch | 0.80 mm |
Ball Count | 472 |
Interconnect | BGA-472 |
|
R-Car M1S is a mid-range performance embedded single-core SoC for the automotive industry designed by Renesas and introduced in 2011. The M1S features a single SH-4A core operating at 800 MHz. This chip incorporates Imagination's PowerVR SGX540 GPU operating at 200 MHz. This SoC supports up to 1 GiB of DDR3-1066 memory.
Introduced early-2011 with samples available in May 2011. Renesas expected mass production to begin in June 2012.
Cache
- Main article: Cortex-A9 § Cache
[Edit/Modify Cache Info]
|
Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.
|
L1$ | 128 KiB 131,072 B 0.125 MiB
| L1I$ | 64 KiB 65,536 B 0.0625 MiB
| 2x32 KiB | 4-way set associative | |
---|
L1D$ | 64 KiB 65,536 B 0.0625 MiB
| 2x32 KiB | 4-way set associative | |
---|
|
---|
|
Memory controller
[Edit/Modify Memory Info]
|
Integrated Memory Controller
|
Max Type | DDR3-1066, DDR2-800 |
---|
Supports ECC | No |
---|
Max Mem | 1 GiB |
---|
Controllers | 1 |
---|
Channels | 1 |
---|
Width | 32 bit |
---|
Max Bandwidth | 3.97 GiB/s 4,065.28 MiB/s 4.263 GB/s 4,262.755 MB/s 0.00388 TiB/s 0.00426 TB/s
|
---|
Bandwidth |
Single 3.97 GiB/s
|
|
Expansions
- MLB (MOST150) 6-Pin I/F
- 2 x CAN 32 Message Buffers
- MMC
- 3 x SD
Graphics
- 20MPoly/s; 1000MPix/s; 3.2GFlops/s
[Edit/Modify IGP Info]
|
Integrated Graphics Information
|
GPU | PowerVR SGX540 |
Designer | Imagination Technologies |
Execution Units | 2 | Max Displays | 2 |
|
Frequency | 200 MHz 0.2 GHz 200,000 KHz
|
---|
| Standards | |
|
Block Diagram
-