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From WikiChip
StrongARM - DEC
< dec
(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)
| StrongARM | |
| |
| A SA-110S model | |
| Developer | DEC, ARM Holdings, Intel |
| Manufacturer | DEC, Intel |
| Type | Microprocessors |
| Architecture | 32-bit embedded ARM processors |
| ISA | ARMv4 |
| µarch | StrongARM |
| Word size | 32 bit 4 octets
8 nibbles |
| Process | 0.35 μm 350 nm , 0.25 μm3.5e-4 mm 250 nm
2.5e-4 mm |
| Technology | CMOS |
| Package | MBGA-256 |
| Succession | |
| → | |
| XScale | |
StrongARM (SA) was a family of 32-bit performance ARM processors for the embedded market designed collaboratively by DEC and ARM.
Retrieved from "https://en.wikichip.org/w/index.php?title=dec/strongarm&oldid=43431"
Facts about "StrongARM - DEC"
| designer | DEC +, ARM Holdings + and Intel + |
| full page name | dec/strongarm + |
| instance of | microprocessor family + |
| instruction set architecture | ARMv4 + |
| main designer | DEC + |
| manufacturer | DEC + and Intel + |
| microarchitecture | StrongARM + |
| name | StrongARM + |
| package | MBGA-256 + |
| process | 350 nm (0.35 μm, 3.5e-4 mm) + and 250 nm (0.25 μm, 2.5e-4 mm) + |
| technology | CMOS + |
| word size | 32 bit (4 octets, 8 nibbles) + |