Xeon W-2150B - Intel

	Edit Values
	Xeon W-2150B
	General Info
Designer	Intel
Manufacturer	Intel
Model Number	W-2150B
Market	Workstation
Introduction	June 5, 2017 (announced); December 21, 2017 (launched)
Shop	Amazon
	General Specs
Family	Xeon W
Series	W-2000
Locked	Yes
Frequency	3,000 MHz
Turbo Frequency	4,500 MHz (1 core),; 4,500 MHz (2 cores),; 4,300 MHz (3 cores),; 4,300 MHz (4 cores),; 4,100 MHz (5 cores),; 4,100 MHz (6 cores),; 4,100 MHz (7 cores),; 4,100 MHz (8 cores),; 3,800 MHz (9 cores),; 3,800 MHz (10 cores)
Bus type	DMI 3.0
Bus rate	4 × 8 GT/s
Clock multiplier	30
	Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Skylake (server)
Platform	Basin Falls
Core Name	Skylake W
Core Family	6
Core Stepping	U0
Process	14 nm
Technology	CMOS
Word Size	64 bit
Cores	10
Threads	20
Max Memory	512 GiB
	Multiprocessing
Max SMP	1-Way (Uniprocessor)
	Packaging
Package	FCLGA-2066 (LGA)
Dimension	52.5 mm × 45 mm
Pitch	1.016 mm
Contacts	2066
Socket	Socket R4

W-2150B is a 64-bit deca-core x86 enterprise performance workstation microprocessor introduced by Intel in 2017. This processors, which is fabricated on an enhanced 14nm+ process based on the Skylake server microarchitecture, operates at 3.0 GHz with a TDP of 120 W and a turbo boost frequency of up to 4.5 GHz. This chip supports up to 512 GiB of quad-channel DDR4-2666 ECC memory.

This specific model appears to be a special model for Apple for their iMac Pros.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

640 KiB

655,360 B
0.625 MiB

L1I$	320 KiB 327,680 B 0.313 MiB	10x32 KiB	8-way set associative	1
L1D$	320 KiB 327,680 B 0.313 MiB	10x32 KiB	8-way set associative	write-back

L2$

10 MiB

10,240 KiB
10,485,760 B
0.00977 GiB

L2I$	1	1	1	1
L2D$	1	1	1	1

L3$

13.75 MiB

14,080 KiB
14,417,920 B
0.0134 GiB

		10x1.375 MiB	11-way set associative	write-back

L4$

1

1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB

		1	1	1

Memory controller

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	DDR4-2666
Supports ECC	Yes
Max Mem	512 GiB
Controllers	2
Channels	4
Max Bandwidth	79.47 GiB/s 81,377.28 MiB/s 85.33 GB/s 85,330.263 MB/s 0.0776 TiB/s 0.0853 TB/s
Bandwidth	Single 19.87 GiB/s Double 39.74 GiB/s Quad 79.47 GiB/s
Physical Address (PAE)	46 bit

Expansions

[Edit/Modify Expansions Info]

Expansion Options

PCIe	Revision: 3.0
	Max Lanes: 48
	Configuration: x16, x8, x4

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX	MMX Extension
EMMX	Extended MMX Extension
SSE	Streaming SIMD Extensions
SSE2	Streaming SIMD Extensions 2
SSE3	Streaming SIMD Extensions 3
SSSE3	Supplemental SSE3
SSE4.1	Streaming SIMD Extensions 4.1
SSE4.2	Streaming SIMD Extensions 4.2
AVX	Advanced Vector Extensions
AVX2	Advanced Vector Extensions 2
AVX-512	Advanced Vector 512-bit (2 Units)
AVX512F	AVX-512 Foundation
AVX512CD	AVX-512 Conflict Detection
AVX512BW	AVX-512 Byte and Word
AVX512DQ	AVX-512 Doubleword and Quadword Instructions
AVX512VL	AVX-512 Vector Length
ABM	Advanced Bit Manipulation
BMI1	Bit Manipulation Instruction Set 1
BMI2	Bit Manipulation Instruction Set 2
FMA3	3-Operand Fused-Multiply-Add
AES	AES Encryption Instructions
RdRand	Hardware RNG
ADX	Multi-Precision Add-Carry
CLMUL	Carry-less Multiplication Extension
F16C	16-bit Floating Point Conversion

x86-16	16-bit x86
x86-32	32-bit x86
x86-64	64-bit x86
Real	Real Mode
Protected	Protected Mode
SMM	System Management Mode
FPU	Integrated x87 FPU
NX	No-eXecute
HT	Hyper-Threading
TBT 2.0	Turbo Boost Technology 2.0
EIST	Enhanced SpeedStep Technology
SST	Speed Shift Technology
TXT	Trusted Execution Technology (SMX)
vPro	Intel vPro
VT-x	VT-x (Virtualization)
VT-d	VT-d (I/O MMU virtualization)
EPT	Extended Page Tables (SLAT)
TSX	Transactional Synchronization Extensions
MPX	Memory Protection Extensions
Secure Key	Secure Key Technology
SMEP	OS Guard Technology
VMD	Volume Management Device
IPT	Identity Protection Technology

Frequencies

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

Mode	Base	Turbo Frequency/Active Cores
Mode	Base	1	2	3	4	5	6	7	8	9	10
Normal	3,000 MHz	4,500 MHz	4,500 MHz	4,300 MHz	4,300 MHz	4,100 MHz	4,100 MHz	4,100 MHz	4,100 MHz	3,800 MHz	3,800 MHz
AVX2		4,000 MHz	4,000 MHz	3,800 MHz	3,800 MHz	3,700 MHz	3,700 MHz	3,700 MHz	3,700 MHz	3,400 MHz	3,400 MHz
AVX512		4,000 MHz	4,000 MHz	3,800 MHz	3,800 MHz	3,200 MHz	3,200 MHz	3,200 MHz	3,200 MHz	3,000 MHz	3,000 MHz

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon W-2150B - Intel#pcie +
base frequency	3,000 MHz (3 GHz, 3,000,000 kHz) +
bus links	4 +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus type	DMI 3.0 +
clock multiplier	30 +
core count	10 +
core family	6 +
core name	Skylake W +
core stepping	U0 +
designer	Intel +
family	Xeon W +
first announced	June 5, 2017 +
first launched	December 21, 2017 +
full page name	intel/xeon w/w-2150b +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Secure Key Technology +, OS Guard + and Identity Protection Technology +
has intel enhanced speedstep technology	true +
has intel identity protection technology support	true +
has intel secure key technology	true +
has intel speed shift technology	true +
has intel supervisor mode execution protection	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	640 KiB (655,360 B, 0.625 MiB) +
l1d$ description	8-way set associative +
l1d$ size	320 KiB (327,680 B, 0.313 MiB) +
l1i$ description	8-way set associative +
l1i$ size	320 KiB (327,680 B, 0.313 MiB) +
l2$ size	10 MiB (10,240 KiB, 10,485,760 B, 0.00977 GiB) +
l2d$ description	1 +
l2d$ size	1 +
l2i$ description	1 +
l2i$ size	1 +
l3$ description	11-way set associative +
l3$ size	13.75 MiB (14,080 KiB, 14,417,920 B, 0.0134 GiB) +
l4$ description	1 +
l4$ size	1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldate	3000 +
main image	+
manufacturer	Intel +
market segment	Workstation +
max cpu count	1 +
max memory	524,288 MiB (536,870,912 KiB, 549,755,813,888 B, 512 GiB, 0.5 TiB) +
max memory bandwidth	79.47 GiB/s (81,377.28 MiB/s, 85.33 GB/s, 85,330.263 MB/s, 0.0776 TiB/s, 0.0853 TB/s) +
max memory channels	4 +
microarchitecture	Skylake (server) +
model number	W-2150B +
name	Xeon W-2150B +
number of avx-512 execution units	2 +
package	FCLGA-2066 +
platform	Basin Falls +
process	14 nm (0.014 μm, 1.4e-5 mm) +
series	W-2000 +
smp max ways	1 +
socket	Socket R4 +
supported memory type	DDR4-2666 +
technology	CMOS +
thread count	20 +
turbo frequency (10 cores)	3,800 MHz (3.8 GHz, 3,800,000 kHz) +
turbo frequency (1 core)	4,500 MHz (4.5 GHz, 4,500,000 kHz) +
turbo frequency (2 cores)	4,500 MHz (4.5 GHz, 4,500,000 kHz) +
turbo frequency (3 cores)	4,300 MHz (4.3 GHz, 4,300,000 kHz) +
turbo frequency (4 cores)	4,300 MHz (4.3 GHz, 4,300,000 kHz) +
turbo frequency (5 cores)	4,100 MHz (4.1 GHz, 4,100,000 kHz) +
turbo frequency (6 cores)	4,100 MHz (4.1 GHz, 4,100,000 kHz) +
turbo frequency (7 cores)	4,100 MHz (4.1 GHz, 4,100,000 kHz) +
turbo frequency (8 cores)	4,100 MHz (4.1 GHz, 4,100,000 kHz) +
turbo frequency (9 cores)	3,800 MHz (3.8 GHz, 3,800,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +
x86/has memory protection extensions	true +

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