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Tiger Lake µarch
General Info
Arch Type	CPU
Designer	Intel
Manufacturer	Intel
Introduction	September 2, 2020
Process	10 nm
Core Configs	2, 4, 6, 8
Pipeline
OoOE	Yes
Speculative	Yes
Reg Renaming	Yes
Stages	14-19
Decode	5-way
Instructions
ISA	x86-64
Cache
L1I Cache	32 KiB/core 8-way set associative
L1D Cache	48 KiB/core 12-way set associative
L2 Cache	1280 KiB/core 20-way set associative
L3 Cache	3 MiB/core 12-way set associative
Cores
Core Names	Tiger Lake U, Tiger Lake H
Succession
Ice Lake (client) Alder Lake
Contemporary
Sapphire Rapids Rocket Lake

Tiger Lake (TGL) is Intel's successor to Ice Lake, a 10nm microarchitecture for mainstream workstations, desktops, and mobile devices.

Codenames

Core	Abbrev	Description	Graphics	Target
Tiger Lake Y	TGL-Y	Extremely low power		2-in-1s detachable, tablets, and computer sticks
Tiger Lake U	TGL-U	Ultra-low Power		Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
Tiger Lake H35	TGL-H35	High-performance Graphics		35W TDP. High mobile performance, mobile workstations
Tiger Lake H	TGL-H	High-performance Graphics		45W TDP. Ultimate mobile performance, mobile gaming, mobile workstations

Process Technology

Main article: Cannon Lake § Process Technology

Tiger Lake will be manufactured on Intel's third generation enhanced 10nm++ process.

History

Intel 2019 and 2020 Roadmap

Tiger Lake was first announced at Intel's 2019 Investor Meeting in May. Tiger Lake was said to succeed Ice Lake in 2020.

Architecture

Not much is known about Tiger Lake's architecture.

Key changes from Ice Lake

• Core
  • Sunny Cove ➡ Willow Cove
    • Implemented POP to PUSH data forwarding, reg->reg and imm->reg (~1 PUSH+POP pair per cycle)
  • Up to 50% larger Level 3 cache - 3MB per core from 2MB per core
  • 2,5x larger Level 2 cache - 1,25MB per core from 512KB per core
• GPU
  • Gen11 ➡ Gen12 (Xe)
  • 1.5x more EUs (96, up from 64)
• Display
  • HDMI 2.1 (from HDMI 2.0b)
• I/O
  • PCIe 4.0 (from 3.0)
• Hardware Telemetry
  • Intel Platform Monitoring Technology provides access to hardware performance, sampling and tracing data.