• cve/cve-2017-5753
  ...is an input validation check that ensures that <code>input</code> doesn't go out of bounds. Once such code segment is identified, the attacker can then ...hed, the microprocessor will issue another cache miss for that address and go and grab that value from memory.
  12 KB (1,869 words) - 10:01, 27 February 2019
• samsung/microarchitectures/m3
  Both pipes for the execution stage go through two scheduling cycles followed by a two register read cycles. Instr
  20 KB (3,149 words) - 10:44, 15 February 2020
• mirc/identifiers/$regex
  ...y be 50 named searches existing at any time, and shows that named searches go into the list-of-50 and are accessed or removed from the list in a case-ins
  6 KB (1,081 words) - 00:11, 11 March 2021
• electronic-grade silicon
  ...n the manufacturing of [[silicon wafers]]. From MGS to EGS, the impurities go from the order of parts per million to the low parts per billion.
  3 KB (425 words) - 07:21, 4 December 2020
• intel/mesh interconnect architecture
  Consider the 5 by 6 example mesh below. For a packet to go from the tile labeled 'Start' to the [[integrated memory controller|IMC]], ...he vertical half ring and placed on the horizontal half ring where it will go west until it reaches the destination tile.
  7 KB (1,071 words) - 12:59, 2 November 2021
• samsung/exynos/8895
  ...amsung|Mongoose 2|l=arch}} [[big cores]] commonly running at 2314 (but can go up to 2808 MHz), 4 {{armh|Cortex-A53|l=arch}} [[little cores]] at 1690 (to
  5 KB (713 words) - 07:19, 16 May 2024
• cavium/microarchitectures/vulcan
  ...m is decomposed into its constituent instructions where they are queued to go for the [[instruction decode|decoder]]. The queue is shared by all threads.
  17 KB (2,449 words) - 22:11, 4 October 2019
• supercomputers/frontier
  ...by the [[DoE]] [[Oak Ridge National Laboratory]]. Frontier is expected to go into operation in the 2021-2022 timeframe.
  2 KB (236 words) - 20:40, 21 July 2019
• thatic
  ...he final chips by using a suiting foundry (e.g., [[TSMC]]). The final dies go back to Haiguang IC Design for packaging and sale. The final chip bears "Ha
  2 KB (283 words) - 09:42, 8 July 2018
• mediatek/helio/mt6762m
  * [[used by::Tecno Spark Go]]
  3 KB (359 words) - 00:19, 14 March 2023
• supercomputers/astra
  ...nodes go directly to the 36-port switch. There are 12 remaining ports that go to the level 2 switches (discussed later). A full rack with 72 nodes has 4,
  8 KB (1,133 words) - 23:36, 2 June 2020
• arm/aarch64
  ...ing progressively more privileged than the one below it. Exceptions always go to the same level or a higher level but they can not take you to a lower le
  4 KB (661 words) - 20:26, 2 May 2019
• intel/configurable spatial accelerator
  ...bric targets in its neighborhood. When this occurs, all PEs are paused and go into an unconfigured state. PEs receive their configuration packet, set it
  14 KB (2,130 words) - 20:19, 2 October 2018
• intel/microarchitectures/sunny cove
  ...scheduler ports that can perform those memory operations. Store operations go to the store buffer which is also capable of performing forwarding when nee
  34 KB (5,187 words) - 06:27, 17 February 2023
• supercomputers/nersc-10
  ...e]] supercomputer currently in pathfinding stages. NERSC-10 is expected to go online around the 2024 timeframe.
  711 bytes (87 words) - 04:44, 10 February 2019
• tesla (car company)/fsd chip
  ...SD chip meets AEC-Q100 Grade-2 automotive quality standards. The choice to go with a mature [[14 nm]] node instead of a more [[technology node|leading-ed
  13 KB (1,952 words) - 20:34, 16 September 2023
• supercomputers/olcf-6
  ...ed by the [[DoE]] [[Oak Ridge National Laboratory]]. OLCF-6 is expected to go into operation in the 2023-2024 timeframe and will feature a peak performan
  821 bytes (110 words) - 13:46, 7 May 2019
• samsung/exynos/990
  ...mory and incorporates a {{armh|Mali-G77}} MP11 GPU. The 990 is designed to go along with Exynos Modem 5123 5G modem.
  4 KB (635 words) - 00:28, 8 November 2023
• centaur/microarchitectures/cha
  ...by the two DMA channels on the ring stop interface. These DMA channels can go out to the other caches or memory asynchronously. On occasion, data may be
  24 KB (3,792 words) - 04:37, 30 September 2022
• cray/microarchitectures/rosetta
  For example, to go from Port18 to Port9, pockets are first routed from Port18 along the row-bu ...s (Output->Input) - A grant is sent back when a pocket has been granted to go; output buffer space is also reserved at that point
  4 KB (588 words) - 05:44, 8 September 2020

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