• intel/microarchitectures/bonnell
  ! First Generation !! !! Second Generation !! !! Third Generation ...mic operations consisting of a single destination register and up to three source-registers (typical load-operate-store format). Most instructions actually c
  38 KB (5,468 words) - 20:29, 23 May 2019
• intel/microarchitectures/saltwell
  * '''Source Operand Read'''
  7 KB (872 words) - 19:42, 30 November 2017
• intel/xeon d
  ...book]] and [[Intel]] in 2013. Yosemite is the codename for Facebook's open source modular chassis for the highly-concurrent but lower-power microservers. The
  13 KB (1,784 words) - 08:04, 6 April 2019
• 16 µm lithography process
  ...This process had an effective channel length of roughly 16 µm between the source and drain (Poly-SI channel implant). The typical [[wafer size]] for this pr
  502 bytes (66 words) - 23:04, 20 May 2018
• 20 µm lithography process
  ...rocess had an effective channel (Alu) length of roughly 20 µm between the source and drain (channel implant). The typical [[wafer]] size for this process wa
  902 bytes (119 words) - 23:04, 20 May 2018
• 50 µm lithography process
  ...rocess had an effective channel (Alu) length of roughly 50 µm between the source and drain. The typical [[wafer]] size for this process at companies such as
  524 bytes (70 words) - 23:04, 20 May 2018
• intel/microarchitectures/sandy bridge (client)
  ** Integrated graphics is now integrated on the same die (previously was on a second die) ** Integrated on-die is now integrated on the same die (previously was on a second die)
  84 KB (13,075 words) - 00:54, 29 December 2020
• intel/microarchitectures/skylake (client)
  ...r Forum in San Francisco on September 9 with the goals of launching in the second half of 2015. ...eived, the first 4 instructions will be processed in the first cycle and a second cycle will be required for the last instruction. This will produce an avera
  79 KB (11,922 words) - 06:46, 11 November 2022
• 3.5 µm lithography process
  ...his process had an effective channel length of roughly 3.5 µm between the source and drain. This process was later superseded by [[3 µm]], [[2 µm]], and [
  1 KB (122 words) - 06:21, 20 July 2018
• microsystems international
  * {{mil|MF7???}}, second source of [[Intel]]'s {{intel|1103}} 1K DRAM * {{mil|MF7114}}, second source/enhanced version of [[Intel]]'s {{intel|4004}}
  2 KB (289 words) - 07:23, 29 April 2016
• amd/am386
  ...ependent developer of x86 [[microprocessor]]s, as opposed to just a second source manufacturer. ...in 1982, but was terminated in 1987 - an agreement that AMD used to second-source Intel's {{intel|8086}}, {{intel|80186}}, and {{intel|80286}}. AMD's argumen
  8 KB (1,077 words) - 14:50, 2 April 2020
• 1982
  * Unknown: AMD introduced the {{amd|Am8086}}, a 2nd source {{intel|8086}}.
  384 bytes (51 words) - 01:54, 2 January 2018
• amd/am286
  | arch = 2nd source 80286 '''Am286''' (AMD 80286) was a [[second-source]]d {{intel|80286|286}} chip designed by [[Intel]] and manufactured by [[AMD
  9 KB (1,192 words) - 01:35, 29 May 2016
• amd/am186
  '''Am186''' (AMD 80186) was a [[second-source]]d {{intel|80186}} chip designed by [[Intel]] and manufactured by [[AMD]].
  5 KB (602 words) - 18:20, 3 June 2016
• amd/am8086
  '''Am8086''' (AMD 8086) was a [[second-source]]d {{intel|8086}} chip designed by [[Intel]] and manufactured by [[AMD]] in ...in the {{ibm|PC}}. IBM required all their manufacturers to have a [[second source]]. Consequently, in [[1981]] Intel renewed their 76 agreement. A year later
  5 KB (616 words) - 14:24, 1 May 2019
• amd/am8086/p8086
  '''P8086''' is a [[second-source]]d {{intel|8086}} designed by Intel and manufactured by [[AMD]] in a 40-pin
  2 KB (223 words) - 15:19, 13 December 2017
• amd/am8086/p8086b
  '''P8086B''' is a [[second-source]]d {{intel|8086}} designed by Intel and manufactured by [[AMD]] in a 40-pin
  2 KB (229 words) - 15:20, 13 December 2017
• amd/am8086/p8086-1
  '''P8086-1''' is a [[second-source]]d {{intel|8086}} designed by Intel and manufactured by [[AMD]] in a 40-pin
  2 KB (230 words) - 15:20, 13 December 2017
• amd/am8086/p8086-2
  '''P8086-2''' is a [[second-source]]d {{intel|8086}} designed by Intel and manufactured by [[AMD]] in a 40-pin
  2 KB (232 words) - 15:20, 13 December 2017
• amd/am8086/p8086-1b
  '''P8086-1B''' is a [[second-source]]d {{intel|8086}} designed by Intel and manufactured by [[AMD]] in a 40-pin
  2 KB (234 words) - 15:20, 13 December 2017

View (previous 20 | next 20) (20 | 50 | 100 | 250 | 500)