• mathstar/arrix
  * 80x [[register file|RFs]] [[File:arrix chip layout.png|600px]]
  4 KB (492 words) - 00:37, 28 June 2016
• intrinsity/fastmath
  ...-point matrix, vector, and scalar data types with dedicated local register file. Data arrays are directly fetched from L2 cache. [[File:eval board.jpg|right|thumb|Evaluation Board]]
  4 KB (464 words) - 17:41, 3 July 2016
• microarchitecture
  ...[[transistors]] and [[resistors]] to more complex units such as [[register file]]s and [[multipliers]] to complete elements such as [[arithmetic logic unit ...or [[VHDL]]. The description of the circuit is known as [[RTL design]]. [[Register Transfer Level]] (RTL) can be efficiently described using HDL. Final RTL de
  3 KB (431 words) - 22:51, 21 November 2017
• amd/microarchitectures/zen
  [[File:amd-zen-black-logo.png|right|Zen Logo]] [[File:amd ryzen black bg logo.png|thumb|right|Ryzen brand logo]]
  79 KB (12,095 words) - 15:27, 9 June 2023
• amd/microarchitectures/zen 2
  [[File:amd zen 2 logo.png|right|thumb|Zen 2]] [[File:amd zen2-3 roadmap.png|thumb|right|Zen 2 on the roadmap]]
  57 KB (8,701 words) - 22:11, 9 October 2022
• intel/microarchitectures/gen9.5
  [[File:iris graphics logo.svg|right|200px]] [[File:kaby lake soc block diagram.svg|900px]]
  29 KB (3,752 words) - 13:14, 19 April 2023
• intel/microarchitectures/gen9
  [[File:iris graphics logo.svg|right|200px]][[File:iris pro graphics logo.svg|right|200px]] [[File:skylake soc block diagram.svg|900px]]
  33 KB (4,255 words) - 17:41, 1 November 2018
• phytium/microarchitectures/xiaomi
  [[File:xiaomi block diagram.svg]] [[File:phytium xiaomi predictor.png|thumb|right|predictor]]
  7 KB (940 words) - 00:12, 8 March 2021
• acorn/microarchitectures/arm1
  [[File:arm1 block diagram.svg|700px]] : [[File:arm1 pipeline.svg|800px]]
  12 KB (1,886 words) - 12:56, 14 January 2021
• amd/microarchitectures/zen 3
  [[File:amd zen future roadmap.jpg|400px|right]] [[File:amd zen2-3 roadmap.png|thumb|right|Zen 3 on the roadmap]]
  15 KB (1,978 words) - 22:13, 6 April 2023
• intel/microarchitectures/merced
  ** REN: Register remapping ** REG: Register file read
  7 KB (978 words) - 21:16, 20 January 2021
• macro-operation fusion
  ...h fewer bits, free up execution units, tracking information (e.g. in the [[register renaming|rename unit]]), save pipeline bandwidth in all stages from decode [[File:core mopf off.png|350px]]
  11 KB (1,614 words) - 23:01, 8 May 2020
• dec/microarchitectures/alpha 21064
  *** 32-entry integer register file *** 32-entry FP register file
  4 KB (527 words) - 02:09, 4 August 2017
• acorn/microarchitectures/arm2
  * 27-entry register file (from 25) [[File:arm2 block diagram.svg|750px]]
  14 KB (2,093 words) - 04:42, 10 July 2018
• acorn/microarchitectures/arm3
  * <code>SWP</code> - Swap word memory-register, Atomic (uninterruptible) : [[File:arm3 block diagram.svg|600px]]
  7 KB (1,035 words) - 06:24, 21 November 2023
• arm holdings/microarchitectures/arm6
  * <code>MRS</code> - Move from register to CPSR/SPSR * <code>MSR</code> - Move from CPSR/SPSR to register
  11 KB (1,679 words) - 21:00, 15 May 2024
• x86/avx-512
  ...nd 64-bit lane for instance refers to bits 64 ... 95 and 96 ... 127 of the register, again counting from the least significant bit. ...tor registers. Accordingly in assembler code the vector size is implied by register names XMM, YMM, and ZMM. AVX-512 instructions can of course access 32 of al
  83 KB (13,667 words) - 15:45, 16 March 2023
• intel/frequency behavior
  .... This table is stored within the read-only processor {{x86|model specific register}} (MSR) and is used to ensure that frequencies do not exceed the lower or u [[File:mixed avx-normal workloads with avx512.png|thumb|right|200px|Cores are grou
  5 KB (797 words) - 01:10, 1 June 2020
• intel/microarchitectures/skylake (server)
  [[File:xeon scalable family decode.png|thumb|right|250px|New Xeon branding]] | [[File:core i7 logo (2015).png|50px|link=intel/core_i7]] || {{intel|Core i7}} || s
  52 KB (7,651 words) - 00:59, 6 July 2022
• intel/microarchitectures/goldmont plus
  | [[File:intel celeron (2015).png|50px|link=intel/celeron]] || {{intel|Celeron}} || | rowspan="2" | [[File:intel pentium silver logo (2017).png|50px|link=intel/pentium_silver]] || ro
  9 KB (1,128 words) - 13:28, 17 July 2023

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