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• ambric/am2000
  * 2x '''RAM Units''' (RU) ::Each RAM Unit contains 4 2 kB RAM banks, each independently accessed via a dynamically programmed channel ope
  11 KB (1,421 words) - 14:45, 9 December 2018
• ambric/am2000/am2045
  ...43 homogeneous 'Brics' laid out in a 5 by 9 grid to form 344 cores and 344 RAM units. ** 2x [[RAM]] Unit (RU)
  3 KB (367 words) - 15:16, 13 December 2017
• ambric/am2000/am2035
  ...ade of 35 homogeneous 'Brics' laid out in a grid to form 280 cores and 280 RAM units. ** 2x [[RAM]] Unit (RU)
  3 KB (280 words) - 15:16, 13 December 2017
• ambric/am2000/am2024
  ...ade of 24 homogeneous 'Brics' laid out in a grid to form 192 cores and 192 RAM units. ** 2x [[RAM]] Unit (RU)
  3 KB (280 words) - 15:16, 13 December 2017
• ambric/am2000/am2012
  ...made of 12 homogeneous 'Brics' laid out in a grid to form 96 cores and 96 RAM units. ** 2x [[RAM]] Unit (RU)
  3 KB (280 words) - 15:16, 13 December 2017
• ambric/am2000/am2045b
  ** 2x [[RAM]] Unit (RU)
  3 KB (344 words) - 15:16, 13 December 2017
• ambric/am2000/am2029
  ** 2x [[RAM]] Unit (RU)
  3 KB (256 words) - 15:16, 13 December 2017
• ambric/am2000/am2016
  ** 2x [[RAM]] Unit (RU)
  3 KB (256 words) - 15:16, 13 December 2017
• ambric/am2000/am2070
  ** 2x [[RAM]] Unit (RU)
  3 KB (256 words) - 15:16, 13 December 2017
• mathstar/builder
  *** Dual-ported RAM, single-cycle access * Internal Block [[RAM]]
  5 KB (596 words) - 21:23, 19 November 2017
• mathstar/arrix
  ** 128 Byte, dualport RAM or FIFO * 12x Internal [[RAM]] banks
  4 KB (492 words) - 00:37, 28 June 2016
• amd/microarchitectures/zen 2
  ...ed number of microcode entry addresses and redirect execution to the patch RAM.
  57 KB (8,701 words) - 22:11, 9 October 2022
• mos technology
  *{{mos|6530}} ROM/RAM I/O Timer (RRIOT) *{{mos|6532}} RAM I/O Timer (RIOT)
  2 KB (269 words) - 18:40, 31 August 2021
• acorn/microarchitectures/arm3
  ...f negligible performance. Each CAM entry refers to one line of data in the RAM. Each line consists of four 32-bit words (i.e., 128 bit lines) with the low ...On a hit the appropriate line address are generated to be retrieved by the RAM.
  7 KB (1,035 words) - 06:24, 21 November 2023
• intel/microarchitectures/goldmont plus
  ** RAM
  9 KB (1,128 words) - 13:28, 17 July 2023
• amd/microarchitectures/zen+
  ...condary storage devices can actually extend to main memory. Up to 2 GiB of RAM may be configured and reserved as another level of cache for the HDD on top
  11 KB (1,613 words) - 08:39, 3 March 2024
• ti/tms1000/tms1099
  ...9JL is a ROM-less version of TMS1000-TMS1200. It has 64 pins, 64x4 bits of RAM, 8 bits of "O" parallel latched data outputs and 13 "R" individually addres
  824 bytes (121 words) - 14:56, 13 December 2017
• ti/tms1000/tms1098
  ...JL is a ROM-less version of TMS1000-TMS1200. It has 64 pins, 128x4 bits of RAM, 8 bits of "O" parallel latched data outputs and 16 "R" individually addres
  900 bytes (128 words) - 14:56, 13 December 2017
• intel/documents
  ...ete offerings of their products including [[microprocessors]], [[ROM]]s, [[RAM]]s, [[memory]] peripherals, and various other [[ICs]].
  4 KB (448 words) - 15:02, 3 October 2019
• greenwaves/gap8
  The chip supports up to 16 MiB of SDRAM or additional RAM through the HyperBus interface. * HyperBus (External Flash and RAM)
  6 KB (981 words) - 14:11, 28 February 2018

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