Edit Values
Xeon Platinum 8260Y
General Info
Designer	Intel
Manufacturer	Intel
Model Number	8260Y
Part Number	CD8069504200902
S-Spec	SRF9F
Market	Server
Introduction	April 2, 2019 (announced) April 2, 2019 (launched)
Release Price	$5,320.00 (tray)
Shop	Amazon
General Specs
Family	Xeon Platinum
Series	8200
Locked	Yes
Frequency	2,400 MHz, 24 Cores, 2,500 MHz, 20 Cores, 2,700 MHz, 16 Cores
Turbo Frequency	3,900 MHz (1 core)
Clock multiplier	24
CPUID	0x50655
Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Cascade Lake
Platform	Purley
Chipset	Lewisburg
Core Name	Cascade Lake SP
Core Family	6
Core Stepping	B1
Process	14 nm
Technology	CMOS
Word Size	64 bit
Cores	24
Threads	48
Max Memory	1 TiB
Multiprocessing
Max SMP	8-Way (Multiprocessor)
Electrical
TDP	165 W
Packaging
Package	FCLGA-3647 (FCLGA)
Dimension	76.16 mm × 56.6 mm
Pitch	0.8585 mm × 0.9906 mm
Contacts	3647
Socket	Socket P, LGA-3647

Xeon Platinum 8260Y is a 64-bit 24-core x86 high-performance server microprocessor introduced by Intel in early 2019. The Platinum 8260Y is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 8-way multiprocessing, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 2.4 GHz with a TDP of 165 W and features a turbo boost frequency of up to 3.9 GHz.

As indicated by the "Y" suffix, this model features Speed Select Technology (SST). It can be configured at 3 different core counts and frequencies - 24 cores, 20 cores, and 16 cores.

Cache

Main article: Cascade Lake § Cache

The Xeon Platinum 8260Y features a larger non-default 35.75 MiB of L3, a size that would normally be found on a 26-core part.

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 1.5 MiB 1,536 KiB 1,572,864 B L1I$ 768 KiB 786,432 B 0.75 MiB 24x32 KiB 8-way set associative   L1D$ 768 KiB 786,432 B 0.75 MiB 24x32 KiB 8-way set associative write-back L2$ 24 MiB 24,576 KiB 25,165,824 B 0.0234 GiB     24x1 MiB 16-way set associative write-back L3$ 35.75 MiB 36,608 KiB 37,486,592 B 0.0349 GiB     26x1.375 MiB 11-way set associative write-back

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR4-2933 Supports ECC Yes Max Mem 1 TiB Controllers 2 Channels 6 Max Bandwidth 131.13 GiB/s 134,277.12 MiB/s 140.8 GB/s 140,799.765 MB/s 0.128 TiB/s 0.141 TB/s Bandwidth Single 21.86 GiB/s Double 43.71 GiB/s Quad 87.42 GiB/s Hexa 131.13 GiB/s

Expansions

[Edit/Modify Expansions Info]

	Expansion Options
PCIe Revision: 3.0 Max Lanes: 48 Configuration: 1x16, x8, x4

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX MMX Extension EMMX Extended MMX Extension SSE Streaming SIMD Extensions SSE2 Streaming SIMD Extensions 2 SSE3 Streaming SIMD Extensions 3 SSSE3 Supplemental SSE3 SSE4.1 Streaming SIMD Extensions 4.1 SSE4.2 Streaming SIMD Extensions 4.2 AVX Advanced Vector Extensions AVX2 Advanced Vector Extensions 2 AVX-512 Advanced Vector 512-bit (2 Units) AVX512F AVX-512 Foundation AVX512CD AVX-512 Conflict Detection AVX512BW AVX-512 Byte and Word AVX512DQ AVX-512 Doubleword and Quadword Instructions AVX512VL AVX-512 Vector Length AVX512_VNNI AVX-512 Vector Neural Network Instructions ABM Advanced Bit Manipulation BMI1 Bit Manipulation Instruction Set 1 BMI2 Bit Manipulation Instruction Set 2 FMA3 3-Operand Fused-Multiply-Add AES AES Encryption Instructions RdRand Hardware RNG ADX Multi-Precision Add-Carry CLMUL Carry-less Multiplication Extension F16C 16-bit Floating Point Conversion x86-16 16-bit x86 x86-32 32-bit x86 x86-64 64-bit x86 Real Real Mode Protected Protected Mode SMM System Management Mode FPU Integrated x87 FPU NX No-eXecute HT Hyper-Threading TBT 2.0 Turbo Boost Technology 2.0 EIST Enhanced SpeedStep Technology SST Speed Shift Technology TXT Trusted Execution Technology (SMX) vPro Intel vPro VT-x VT-x (Virtualization) VT-d VT-d (I/O MMU virtualization) EPT Extended Page Tables (SLAT) TSX Transactional Synchronization Extensions VMD Volume Management Device NM Node Manager KPT Key Protection Technology PTT Platform Trust Technology Run Sure Run Sure Technology (RAS Capability) MBE Ctrl Mode-Based Execute Control Node Ctrlr Node Controller Support DL Boost Deep Learning Boost

Frequencies

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

Mode	Base	Turbo Frequency/Active Cores
		1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24
Normal	2,400MHz	3,900MHz	3,900MHz	3,700MHz	3,700MHz	3,600MHz	3,600MHz	3,600MHz	3,600MHz	3,600MHz	3,600MHz	3,600MHz	3,600MHz	3,600MHz	3,600MHz	3,600MHz	3,600MHz	3,300MHz	3,300MHz	3,300MHz	3,300MHz	3,100MHz	3,100MHz	3,100MHz	3,100MHz
AVX2	1,900MHz	3,700MHz	3,700MHz	3,500MHz	3,500MHz	3,400MHz	3,400MHz	3,400MHz	3,400MHz	3,300MHz	3,300MHz	3,300MHz	3,300MHz	3,000MHz	3,000MHz	3,000MHz	3,000MHz	2,700MHz	2,700MHz	2,700MHz	2,700MHz	2,600MHz	2,600MHz	2,600MHz	2,600MHz
AVX512	1,500MHz	3,700MHz	3,700MHz	3,500MHz	3,500MHz	3,400MHz	3,400MHz	3,400MHz	3,400MHz	3,000MHz	3,000MHz	3,000MHz	3,000MHz	2,600MHz	2,600MHz	2,600MHz	2,600MHz	2,400MHz	2,400MHz	2,400MHz	2,400MHz	2,300MHz	2,300MHz	2,300MHz	2,300MHz