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Xeon Platinum 8260Y - Intel
Edit Values | |
Xeon Platinum 8260Y | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 8260Y |
Market | Server |
Introduction | December 2018 (announced) December 2018 (launched) |
Shop | Amazon |
General Specs | |
Family | Xeon Platinum |
Series | 8000 |
Frequency | 2,400 MHz |
Turbo Frequency | 3,900 MHz (1 core) |
Clock multiplier | 24 |
CPUID | 0x50655 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Cascade Lake |
Platform | Purley |
Chipset | Lewisburg |
Core Name | Cascade Lake SP |
Core Family | 6 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 24 |
Threads | 48 |
Multiprocessing | |
Max SMP | 8-Way (Multiprocessor) |
Electrical | |
TDP | 165 W |
Packaging | |
Template:packages/intel/fclga-3647 |
Xeon Platinum 8260Y is a 64-bit 24-core x86 multi-socket highest performance server microprocessor expected to be introduced by Intel in late 2018. This chip supports up to 8-way multiprocessing. The Platinum 8260Y, which is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm++ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 2.3 GHz with a TDP of 165 W and a turbo boost frequency of up to 3.9 GHz, supports up ? GiB of hexa-channel DDR4-2666 memory.
Contents
Cache
- Main article: Cascade Lake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
Expansion Options
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Features
[Edit/Modify Supported Features]
Facts about "Xeon Platinum 8260Y - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Platinum 8260Y - Intel#pcie + |
base frequency | 2,400 MHz (2.4 GHz, 2,400,000 kHz) + |
chipset | Lewisburg + |
clock multiplier | 24 + |
core count | 24 + |
core family | 6 + |
core name | Cascade Lake SP + |
core stepping | B0 + and B1 + |
cpuid | 0x50655 + |
designer | Intel + |
family | Xeon Platinum + |
first announced | April 2, 2019 + |
first launched | April 2, 2019 + |
full page name | intel/xeon platinum/8260y + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Encryption Standard Instruction Set Extension +, Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Deep Learning Boost +, Enhanced SpeedStep Technology +, Extended Page Tables +, Hyper-Threading Technology +, Intel VT-d +, Intel VT-x +, Intel vPro Technology +, Speed Shift Technology +, Transactional Synchronization Extensions +, Trusted Execution Technology + and Turbo Boost Technology 2.0 + |
has intel deep learning boost | true + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 1,536 KiB (1,572,864 B, 1.5 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 768 KiB (786,432 B, 0.75 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 768 KiB (786,432 B, 0.75 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 24 MiB (24,576 KiB, 25,165,824 B, 0.0234 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 35.75 MiB (36,608 KiB, 37,486,592 B, 0.0349 GiB) + |
ldate | April 2, 2019 + |
main image | + |
manufacturer | Intel + |
market segment | Server + |
max cpu count | 8 + |
max memory | 1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) + |
max memory bandwidth | 131.13 GiB/s (134,277.12 MiB/s, 140.8 GB/s, 140,799.765 MB/s, 0.128 TiB/s, 0.141 TB/s) + |
max memory channels | 6 + |
microarchitecture | Cascade Lake + |
model number | 8260Y + |
name | Xeon Platinum 8260Y + |
number of avx-512 execution units | 2 + |
package | FCLGA-3647 + |
part number | CD8069504200902 + |
platform | Purley + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 5,320.00 (€ 4,788.00, £ 4,309.20, ¥ 549,715.60) + |
release price (tray) | $ 5,320.00 (€ 4,788.00, £ 4,309.20, ¥ 549,715.60) + |
s-spec | SRF9F + |
s-spec (qs) | QRC1 + |
series | 8200 + |
smp interconnect | UPI + |
smp interconnect links | 3 + |
smp interconnect rate | 10.4 GT/s + |
smp max ways | 8 + |
socket | LGA-3647 + and Socket P + |
supported memory type | DDR4-2933 + |
tdp | 165 W (165,000 mW, 0.221 hp, 0.165 kW) + |
technology | CMOS + |
thread count | 48 + |
turbo frequency (1 core) | 3,900 MHz (3.9 GHz, 3,900,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |