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From WikiChip
Palm Cove - Microarchitectures - Intel
< intel | microarchitectures
| Edit Values | |
| Palm Cove µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2018 |
| Process | 10 nm |
| Instructions | |
| ISA | x86-64 |
| Succession | |
Palm Cove is a high-performance 10 nm x86 core microarchitecture designed by Intel for an array of server and client products.
Process Technology
Palm Cove is designed to take advantage of Intel's 10 nm process.
Architecture
Key changes from Skylake (Server)
 |
Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release. |
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/palm_cove&oldid=86382"
Facts about "Palm Cove - Microarchitectures - Intel"
| codename | Palm Cove + |
| core count | 2 + |
| designer | Intel + |
| first launched | 2018 + |
| full page name | intel/microarchitectures/palm cove + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Palm Cove + |
| pipeline stages (max) | 19 + |
| pipeline stages (min) | 14 + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |