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Cortex-A76 µarch
General Info
Arch Type	CPU
Designer	ARM Holdings
Manufacturer	TSMC
Introduction	May 31, 2018
Process	10 nm, 7 nm
Core Configs	1, 2, 4
Pipeline
OoOE	Yes
Speculative	Yes
Reg Renaming	Yes
Stages	11-13
Decode	4-way
Instructions
ISA	ARMv8.2
Extensions	FPU, NEON
Cache
L1I Cache	64 KiB/core 4-way set associative
L1D Cache	64 KiB/core 4-way set associative
L2 Cache	256-512 KiB/core 8-way set associative
L3 Cache	0-4 MiB/Cluster
Succession
Cortex-A75 Deimos
Contemporary
Ares

Cortex-A76 (codename Enyo) is the successor to the Cortex-A75, a low-power high-performance ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A76, which implemented the ARMv8.2 ISA, is the a performant core which is often combined with a number of lower power cores (e.g. Cortex-A55) in a DynamIQ big.LITTLE configuration to achieve better energy/performance.

Architecture

Block Diagram

Typical SoC

Individual Core

Memory Hierarchy

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Overview

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Core

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Overview

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Pipeline

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Bibliography

• Arm Tech Day, 2018