From WikiChip
Hi1620 - HiSilicon
Edit Values | |
Hi1620 | |
General Info | |
Designer | HiSilicon, ARM Holdings |
Manufacturer | TSMC |
Model Number | Hi1620 |
Market | Server |
Introduction | September, 2018 (announced) September, 2018 (launched) |
General Specs | |
Family | Hi16xx |
Frequency | 3,000 MHz |
Microarchitecture | |
ISA | ARMv8 (ARM) |
Microarchitecture | Ares |
Core Name | Ares |
Technology | CMOS |
Word Size | 64 bit |
Cores | 48 |
Threads | 48 |
Max Memory | 512 GiB |
Multiprocessing | |
Max SMP | 2-Way (Multiprocessor) |
Hi1620 is a planned octatetraconta-core 64-bit ARM server microprocessor set to be introduced by HiSilicon in late-2018. Fabricated by TSMC on a 7 nm process, this chip incorporates 64 Ares cores operating at up to 3 GHz. The Hi1620 supports up to 1 TiB of octa-channel DDR4-3200 memory.
Cache
- Main article: Ares § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options |
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Features
[Edit/Modify Supported Features]
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Supported ARM Extensions & Processor Features
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Utilizing devices
- HiSilicon D06
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Facts about "Kunpeng 920-6426 - HiSilicon"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Kunpeng 920-6426 - HiSilicon#pcie + |
base frequency | 3,000 MHz (3 GHz, 3,000,000 kHz) + |
core count | 48 + |
core name | Ares + |
designer | HiSilicon + and ARM Holdings + |
family | Hi16xx + |
first announced | September 2018 + |
first launched | September 2018 + |
full page name | hisilicon/kunpeng/920-6426 + |
has ecc memory support | true + |
instance of | microprocessor + |
isa | ARMv8 + |
isa family | ARM + |
l1$ size | 8,192 KiB (8,388,608 B, 8 MiB) + |
l1d$ size | 4,096 KiB (4,194,304 B, 4 MiB) + |
l1i$ size | 4,096 KiB (4,194,304 B, 4 MiB) + |
l2$ size | 32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) + |
l3$ size | 64 MiB (65,536 KiB, 67,108,864 B, 0.0625 GiB) + |
ldate | 3000 + |
manufacturer | TSMC + |
market segment | Server + |
max cpu count | 2 + |
max memory | 524,288 MiB (536,870,912 KiB, 549,755,813,888 B, 512 GiB, 0.5 TiB) + |
max memory bandwidth | 190.7 GiB/s (195,276.8 MiB/s, 204.763 GB/s, 204,762.566 MB/s, 0.186 TiB/s, 0.205 TB/s) + |
max memory channels | 8 + |
max sata ports | 2 + |
max usb ports | 4 + |
microarchitecture | Ares + |
model number | Hi1620 + |
name | Hi1620 + |
smp max ways | 2 + |
supported memory type | DDR4-3200 + |
technology | CMOS + |
thread count | 48 + |
used by | HiSilicon D06 + |
word size | 64 bit (8 octets, 16 nibbles) + |