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Carmel - Microarchitectures - Nvidia
Edit Values | |
Carmel µarch | |
General Info | |
Arch Type | CPU |
Designer | Nvidia |
Manufacturer | TSMC |
Introduction | January 7, 2018 |
Process | 12 nm |
Core Configs | 8 |
Pipeline | |
Type | Superscalar |
OoOE | Yes |
Speculative | Yes |
Reg Renaming | Yes |
Instructions | |
ISA | ARMv8 |
Cache | |
L2 Cache | 2 MiB/cluster |
L3 Cache | 4 MiB/complex |
Succession | |
Carmel is a the successor to Denver 2, an ARM microarchitecture for Nvidia's Tegra series of SoCs.
Contents
Architecture
Nvidia disclosed very few details regarding Carmel.
- 12 nm (12FF)
- ARMv8.2 (Only AArch64)
- ARM RAS standard support
- Eight-core cluster
- 4x Core duplexes
Memory Hierarchy
- Cache
- L1
- L2
- 2 MiB
- Shared per duplex
- 2 MiB
- L3
- 4 MiB
- Shared by entire cluster
- Exclusive
- 4 MiB
Overview
Carmel is a CPU microarchitecture designed by Nvidia for their SoCs. The design consists of an 8-core cluster made of 4 core duplexes. The entire complex has cache coherency as well as an I/O coherent memory subsystem which is designed for communication with the various other accelerators on their SoCs such as the vision accelerator, deep learning accelerator, multimedia engine, and the GPU.
Die
CPU Complex
- 8 cores
- 4 duplexes
- shared L3
- ~62.25 mm² die size area
CPU Duplex
- 2 cores
- ~11.4 mm² die size area
Core
- ~5.75 mm² die size area
Bibliography
- IEEE Hot Chips 30 Symposium (HCS) 2018.
Facts about "Carmel - Microarchitectures - Nvidia"
codename | Carmel + |
core count | 8 + |
designer | Nvidia + |
first launched | January 7, 2018 + |
full page name | nvidia/microarchitectures/carmel + |
instance of | microarchitecture + |
instruction set architecture | ARMv8 + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Carmel + |
process | 12 nm (0.012 μm, 1.2e-5 mm) + |