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Post-K - Microarchitectures - Fujitsu
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Post-K µarch
General Info
Arch TypeCPU
DesignerFujitsu
ManufacturerTSMC
Introduction2018
Core Configs52
Pipeline
TypeSuperscalar, Superpipeline
OoOEYes
SpeculativeYes
Reg RenamingYes
Instructions
ISAARMv8
ExtensionsSVE

Post-K is an ARM microarchitecture designed by Fujitsu for the Post-K


Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

Architecture

Post-K is a custom-designed Template:Arch ARM microprocessor.

  • ARMv8-A
    • SVE Extension
      • Supports 512-bit vector operations
  • Many-core Architecture
    • 52-cores/chip
      • 48 compute cores + assistant cores
  • Memory
    • 3D stacked DRAM (HBM 3/4?)
      • Terabyte/s BW
Retrieved from "https://en.wikichip.org/w/index.php?title=fujitsu/microarchitectures/post-k&oldid=79579"
Facts about "Post-K - Microarchitectures - Fujitsu"
RDF feed
codenamePost-K +
core count52 +
designerFujitsu +
first launched2018 +
full page namefujitsu/microarchitectures/post-k +
instance ofmicroarchitecture +
instruction set architectureARMv8 +
manufacturerTSMC +
microarchitecture typeCPU +
namePost-K +