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ThunderX2 CN9965
General Info
Designer	Cavium
Manufacturer	TSMC
Model Number	CN9965
Part Number	CN9965-2500LG4077-Y21-G, CN9965-2400LG4077-Y21-G, CN9965-2300LG4077-Y21-G, CN9965-2200LG4077-Y21-G, CN9965-2100LG4077-Y21-G, CN9965-2000LG4077-Y21-G
Market	Server
Introduction	May 7, 2018 (announced) May 7, 2018 (launched)
General Specs
Family	ThunderX2
Frequency	1,800 MHz, 2,000 MHz, 2,100 MHz, 2,200 MHz
Microarchitecture
ISA	ARMv8.1 (ARM)
Microarchitecture	Vulcan
Process	16 nm
Technology	CMOS
Word Size	64 bit
Cores	20
Threads	40
Max Memory	2 TiB
Multiprocessing
Max SMP	2-Way (Multiprocessor)
Packaging
Package	FCLGA-4077 (LGA)
Contacts	4077

ThunderX2 CN9965 is a 64-bit icosa-core high-performance ARM server microprocessor introduced by Cavium in mid-2018. The microprocessor, which is based on the Vulcan microarchitecture, is fabricated on TSMC's 16 nm process. Depending on the exact SKU, the CN9965 operates between 1.8 GHz and 2.5 GHz and supports up to quad-/hexa-channel DDR4-2666 memory.

Cache

Main article: Vulcan § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 1.25 MiB 1,280 KiB 1,310,720 B L1I$ 640 KiB 655,360 B 0.625 MiB 20x32 KiB 8-way set associative   L1D$ 640 KiB 655,360 B 0.625 MiB 20x32 KiB 8-way set associative   L2$ 5 MiB 5,120 KiB 5,242,880 B 0.00488 GiB     20x256 KiB 8-way set associative   L3$ 20 MiB 20,480 KiB 20,971,520 B 0.0195 GiB     20x1 MiB