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EPYC Embedded 3251
General Info
Designer	AMD
Manufacturer	GlobalFoundries
Model Number	3251
Market	Server, Embedded
Introduction	February 21, 2018 (announced) February 21, 2018 (launched)
Shop	Amazon
General Specs
Family	EPYC Embedded
Series	3000
Frequency	2,500 MHz
Turbo Frequency	3,100 MHz (1 core)
Clock multiplier	25
Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Zen
Core Name	Snowy Owl
Process	14 nm
Transistors	4,800,000,000
Technology	CMOS
Die	213 mm²
Word Size	64 bit
Cores	8
Threads	16
Max Memory	512 GiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
TDP	50 W
Tjunction	0 °C – 105 °C
Packaging
Template:packages/amd/package sp4r2

EPYC Embedded 3251 is a 64-bit octa-core x86 embedded microprocessor introduced by AMD in early 2018 for dense servers and edge devices. Fabricated on a 14 nm process based on the Zen microarchitecture, this chip operates at 2.5 GHz with a TDP of 50 W and a turbo frequency of 3.1 GHz. The 3251 supports up to 512 GiB of dual-channel DDR4-2666 ECC memory.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Zen § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 768 KiB 786,432 B 0.75 MiB L1I$ 512 KiB 524,288 B 0.5 MiB 8x64 KiB 4-way set associative   L1D$ 256 KiB 262,144 B 0.25 MiB 8x32 KiB 8-way set associative write-back L2$ 4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB     8x512 KiB 8-way set associative write-back L3$ 16 MiB 16,384 KiB 16,777,216 B 0.0156 GiB     2x8 MiB 16-way set associative write-back

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR4-2666 Supports ECC Yes Max Mem 512 GiB Controllers 2 Channels 2 Max Bandwidth 39.74 GiB/s 40,693.76 MiB/s 42.671 GB/s 42,670.5 MB/s 0.0388 TiB/s 0.0427 TB/s Bandwidth Single 19.87 GiB/s Double 39.74 GiB/s

Expansions

The EPYC Embedded 3251 has 32 PCIe lanes that are MUX'ed with a number of other ports and can be reconfigured as either SATA ports (up to 8 such ports), or as GbE ports (up to 4 such ports), or any mixed configuration of those options.

[Edit/Modify Expansions Info]

	Expansion Options
PCIe Revision: 3.0 Max Lanes: 32 Configuration: x16, x8, x4, x2 SATA Revision: 3.0 Max Ports: 8

[Edit/Modify Network Info]

	Networking
	Ethernet 10GbE Yes (Ports: 4)