From WikiChip
K3V2E - HiSilicon
< hisilicon‎ | k3
Revision as of 21:43, 6 September 2017 by Inject (talk | contribs)

Template:mpu K3V2E is a 32-bit quad-core mobile ARM microprocessor introduced by HiSilicon in 2013. This chip, which is fabricated on a 40 nm process, incorporates four Cortex-A9 cores operating at 1.5 GHz. The K3V2 integrated Vivante's GC4000 (16 cores) IGP and supports up to 2 channels of LPDDR2-900 memory. The K3V2E is an enhanced version of the K3V2, although the exact changes are not well-documented.


Cache

Main article: Cortex-A9 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB4-way set associative 
L1D$128 KiB
131,072 B
0.125 MiB
4x32 KiB4-way set associative 
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  1x1 MiB8-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR2-900
Supports ECCNo
Controllers1
Channels2
Width32 bit
Max Bandwidth6.71 GiB/s
6,871.04 MiB/s
7.205 GB/s
7,204.808 MB/s
0.00655 TiB/s
0.0072 TB/s
Bandwidth
Single 3.35 GiB/s
Double 6.71 GiB/s

Graphics

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUGC4000
DesignerVivante
Execution Units16Max Displays1
Frequency480 MHz
0.48 GHz
480,000 KHz
OutputDSI
Max Resolution
DSI1920x1200
Standards
DirectX11
OpenGL3.0
OpenCL1.2
OpenGL ES3.1
OpenVG1.1

Expansions

  • 4x high-speed UART interfaces
  • 2x SPI
  • 2x I2C + 2x I2C for camera
  • USB 2.0 On-The-Go (HS OTG) PHY
  • USB 1.1
  • 2x MMC/SD/SDIO interface
  • 22x GPIOs
  • 10 Timers

Block Diagram

hisilicon k3v2 block.png

Utilizing devices

  • Huawei HN3-U01
  • Huawei Ascend P6 (P6-C00)
  • Ascend W2 (W2‐T00)
  • Huawei Honor 3

This list is incomplete; you can help by expanding it.

Retrieved from "https://en.wikichip.org/w/index.php?title=hisilicon/k3/k3v2e&oldid=63701"
Facts about "K3V2E - HiSilicon"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
K3V2E - HiSilicon#package +
base frequency1,500 MHz (1.5 GHz, 1,500,000 kHz) +
core count4 +
core nameCortex-A9 +
designerHiSilicon + and ARM Holdings +
familyK3 +
first announced2013 +
first launched2013 +
full page namehisilicon/k3/k3v2e +
has ecc memory supportfalse +
instance ofmicroprocessor +
integrated gpuGC4000 +
integrated gpu base frequency480 MHz (0.48 GHz, 480,000 KHz) +
integrated gpu designerVivante +
integrated gpu execution units16 +
isaARMv7 +
isa familyARM +
l1$ size256 KiB (262,144 B, 0.25 MiB) +
l1d$ description4-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description4-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description8-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldate2013 +
manufacturerTSMC +
market segmentMobile +
max cpu count1 +
max memory bandwidth6.71 GiB/s (6,871.04 MiB/s, 7.205 GB/s, 7,204.808 MB/s, 0.00655 TiB/s, 0.0072 TB/s) +
max memory channels2 +
microarchitectureCortex-A9 +
model numberK3V2E +
nameK3V2E +
packageTFBGA-576 +
part numberHi3620 +
process40 nm (0.04 μm, 4.0e-5 mm) +
smp max ways1 +
supported memory typeLPDDR2-900 +
technologyCMOS +
thread count4 +
transistor count600,000,000 +
used byHuawei HN3-U01 +, Huawei Ascend P6 +, Ascend W2 + and Huawei Honor 3 +
word size32 bit (4 octets, 8 nibbles) +