Template:mpu W-2125 is a 64-bit quad-core x86 enterprise performance workstation microprocessor introduced by Intel in 2017. This processors, which is fabricated on an enhanced 14nm+ process based on the Skylake server microarchitecture, operates at 4 GHz with a TDP of 120 W and a turbo boost frequency of up to 4.5 GHz. This chip supports up to 512 GiB of hexa-channel DDR4-2666 ECC memory.

Cache

Main article: Skylake § Cache

Note that while this is a quad-core part, the L3 cache size is that of a hexa-core part.

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 256 KiB 262,144 B 0.25 MiB L1I$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB 8-way set associative   L1D$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB 8-way set associative write-back L2$ 4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB     4x1 MiB 16-way set associative write-back L3$ 8.25 MiB 8,448 KiB 8,650,752 B 0.00806 GiB     6x1.375 MiB 11-way set associative write-back