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From WikiChip
StrongARM - Microarchitectures - DEC
< dec
| Edit Values | |
| StrongARM µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | DEC, ARM Holdings |
| Manufacturer | DEC |
| Introduction | February 5, 1996 |
| Process | 0.35 µm |
| Core Configs | 1 |
| Pipeline | |
| OoOE | No |
| Speculative | No |
| Reg Renaming | No |
| Stages | 5 |
| Decode | 1-way |
| Instructions | |
| ISA | ARMv4 |
| Cache | |
| L1I Cache | 16 KiB/core 32-way set associative |
| L1D Cache | 16 KiB/core 32-way set associative |
| Succession | |
Retrieved from "https://en.wikichip.org/w/index.php?title=dec/microarchitectures/strongarm&oldid=43439"
Facts about "StrongARM - Microarchitectures - DEC"
| codename | StrongARM + |
| core count | 1 + |
| designer | DEC + and ARM Holdings + |
| first launched | February 5, 1996 + |
| full page name | dec/microarchitectures/strongarm + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv4 + |
| manufacturer | DEC + and Intel + |
| microarchitecture type | CPU + |
| name | StrongARM + |
| pipeline stages | 5 + |
| process | 350 nm (0.35 μm, 3.5e-4 mm) + |