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Silvermont µarch

General Info

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Silvermont is Intel's 22 nm microarchitecture for the Atom family of system on chips. Introduced in 2013, Silvermont was the successor to Saltwell, targeting smartphones, tablets, embedded devices, and consumer electronics.

Codenames

Platform	Core	Target
Merrifield	Tangier	Smartphones
Moorefield	Tangier	High-end Smartphones
Bay Trail	Valleyview	Tablets
Edisonville	Avoton	Microservers
Edisonville	Rangeley	Embedded Networking

Architecture

Silvermont introduced a number of significant changes from the previous Atom microarchitecture in addition to the increase performance and lower power consumption.

Key changes from Saltwell

• Pipeline is now OoOE
• 14 stage (2 shorter)
• 10 stage panelty for miss (3 shorter)
• Support up to Westmere
• Multi-core modular system (up to 8 cores)

Block Diagram

Core Modules

Silvermont employees a modular core design. Each module consists of 2 cores and 2 threads with exclusive hardware - resources are not shared. Within each module is a 1 MB L2 cache shared between the two cores. The L1 is still identical to Saltwell's: 32K L1I$ and 24K L1D$. Each module as a dedicated point-to-point interface (IDI) to the system agent. Each module has a per-core frequency and power management support. This is a departure from previous microarchitectures as well as similar desktop (e.g. Core) where all cores are tied to the same frequency.

System Agent

The system agent (Silvermont System Agent') acts very much like a North Bridge however it does a much better job than previous Atom microarchitectures performance-wise because it's capable of reordering all requests from all consumers (e.g. Core, GPU).

IDI

While the previous Atom architecture did away with the memory controller by integrating and other support chips on-die, it still used a Front Side Bus implementation to talk to North Bridge. In Silvermont, this was replaced with a lightweight in-die interconnect (IDI) - same one used in the Core processors. The use of IDI should have noticeable performance impact per thread.

Memory Hierarchy

• Cache
  • Hardware prefetchers
  • L1 Cache:
    • 32 KB 8-way set associative instruction, 64 B line size
    • 24 KB 6-way set associative data, 64 B line size
    • Per core
  • L2 Cache:
    • 1 MB 16-way set associative, 64 B line size
    • Per 2 cores
  • L3 Cache:
    • No level 3 cache
  • RAM
    • Maximum of 1GB, 2 GB, and 4 GB
    • dual 32-bit channels, 1 or 2 ranks per channel

Multithreading

Silvermont dropped support for Intel Hyper-Threading Technology.

Pipeline

While Silvermont share some similarities with Saltwell, it introduces a number of significant changes that sets it apart from part Atom microarchitectures. Like Saltwell, the pipeline is still uses a dual-issue design; however it has a pipeline that is 2 stages shorter with a branch misprediction penalty of 3 cycles lower. Silvermont is the first microarchitecture to introduce out-of-order execution (OoOE)

Silvermont pipeline decodes and issues 2 instructions and dispatches 5 operations/cycle.

Instruction Fetch

Instruction Fetch, just like in previous microarchs make up the first three stages of the pipeline. However, with the introduction of out-of-order execution, silvermont's more aggressive fetching and branch prediction mean stalled instructions do not clog the entire pipeline as it did in Saltwell.

Instruction Decode

In previous generations of microarchitectures, common software code had roughly 5% of instructions split up into micro-ops. In Silvermont this is reduced down to just 1-2%. This reduction translates directly into performance because it eliminates the 3-4 additional cycles of overhead. Silvermont has a second branch predictor that can make more accurate predictions based on previously unknown information (e.g. target address from memory or register) and override the generic predictor. Nevertheless the expense of branch misprediction penalties was also reduced by 3 stages (down to 10 cycles from 13 in Saltwell).

Branch Prediction

Silvermont has two branch predictions: one that controls the instruction fetching and a second one that can override the first during the decode stage after gather additional information. The second predictor controls the speculative instruction issuing. For the first predictor, Silvermont uses a Branch Target Buffer to determine the next fetch address which also includes a 4-entry Return Stack Buffer for calls and returns handling.

Die

8-core Avoton Die:

Cores

• Tangier - SoCs for Smartphones
• Valleyview - SoCs for Tablets
• Avoton - SoCs for Microservers
• Rangeley - SoCs for Embedded Networking

All Silvermont Chips

Silvermont Chips
Main processor									IGP
Model	µarch	Platform	Core	Launched	SDP	TDP	Freq	Max Mem	Name	Freq	Max Freq
x3-C3130	Silvermont	SoFIA	SoFIA	4 March 2015			1,000 MHz 1 GHz 1,000,000 kHz		Mali-400 MP2	480 MHz 0.48 GHz 480,000 KHz
x3-C3200RK	Silvermont	SoFIA	SoFIA	4 March 2015	2 W 2,000 mW 0.00268 hp 0.002 kW		1,100 MHz 1.1 GHz 1,100,000 kHz	2,048 MiB 2,097,152 KiB 2,147,483,648 B 2 GiB 0.00195 TiB	Mali-450 MP4	600 MHz 0.6 GHz 600,000 KHz
x3-C3230RK	Silvermont	SoFIA	SoFIA	4 March 2015	2 W 2,000 mW 0.00268 hp 0.002 kW		1,100 MHz 1.1 GHz 1,100,000 kHz	2,048 MiB 2,097,152 KiB 2,147,483,648 B 2 GiB 0.00195 TiB	Mali-450 MP4	600 MHz 0.6 GHz 600,000 KHz
x3-C3405	Silvermont	SoFIA	SoFIA	April 2015	2 W 2,000 mW 0.00268 hp 0.002 kW		1,200 MHz 1.2 GHz 1,200,000 kHz	2,048 MiB 2,097,152 KiB 2,147,483,648 B 2 GiB 0.00195 TiB	Mali T720 MP2	456 MHz 0.456 GHz 456,000 KHz
x3-C3445	Silvermont	SoFIA	SoFIA	April 2015	2 W 2,000 mW 0.00268 hp 0.002 kW		1,200 MHz 1.2 GHz 1,200,000 kHz	2,048 MiB 2,097,152 KiB 2,147,483,648 B 2 GiB 0.00195 TiB	Mali T720 MP2	456 MHz 0.456 GHz 456,000 KHz