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Xeon W-2150B
General Info
Designer	Intel
Manufacturer	Intel
Model Number	W-2150B
Market	Workstation
Introduction	June 5, 2017 (announced) December 21, 2017 (launched)
Shop	Amazon
General Specs
Family	Xeon W
Series	W-2000
Locked	Yes
Frequency	3,000 MHz
Turbo Frequency	4,500 MHz (1 core), 4,500 MHz (2 cores), 4,300 MHz (3 cores), 4,300 MHz (4 cores), 4,100 MHz (5 cores), 4,100 MHz (6 cores), 4,100 MHz (7 cores), 4,100 MHz (8 cores), 3,800 MHz (9 cores), 3,800 MHz (10 cores)
Bus type	DMI 3.0
Bus rate	4 × 8 GT/s
Clock multiplier	30
Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Skylake (server)
Platform	Basin Falls
Core Name	Skylake W
Core Family	6
Core Stepping	U0
Process	14 nm
Technology	CMOS
Word Size	64 bit
Cores	10
Threads	20
Max Memory	512 GiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Packaging
Package	FCLGA-2066 (LGA)
Dimension	52.5 mm × 45 mm
Pitch	1.016 mm
Contacts	2066
Socket	Socket R4

W-2150B is a 64-bit deca-core x86 enterprise performance workstation microprocessor introduced by Intel in 2017. This processors, which is fabricated on an enhanced 14nm+ process based on the Skylake server microarchitecture, operates at 3.0 GHz with a TDP of 120 W and a turbo boost frequency of up to 4.5 GHz. This chip supports up to 512 GiB of quad-channel DDR4-2666 ECC memory.

This specific model appears to be a special model for Apple for their iMac Pros.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 640 KiB 655,360 B 0.625 MiB L1I$ 320 KiB 327,680 B 0.313 MiB 10x32 KiB 8-way set associative   L1D$ 320 KiB 327,680 B 0.313 MiB 10x32 KiB 8-way set associative write-back L2$ 10 MiB 10,240 KiB 10,485,760 B 0.00977 GiB     10x1 MiB 16-way set associative write-back L3$ 13.75 MiB 14,080 KiB 14,417,920 B 0.0134 GiB     10x1.375 MiB 11-way set associative write-back

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR4-2666 Supports ECC Yes Max Mem 512 GiB Controllers 2 Channels 4 Max Bandwidth 79.47 GiB/s 81,377.28 MiB/s 85.33 GB/s 85,330.263 MB/s 0.0776 TiB/s 0.0853 TB/s Bandwidth Single 19.87 GiB/s Double 39.74 GiB/s Quad 79.47 GiB/s Physical Address (PAE) 46 bit

Expansions

[Edit/Modify Expansions Info]

	Expansion Options
PCIe Revision: 3.0 Max Lanes: 48 Configuration: x16, x8, x4

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX MMX Extension EMMX Extended MMX Extension SSE Streaming SIMD Extensions SSE2 Streaming SIMD Extensions 2 SSE3 Streaming SIMD Extensions 3 SSSE3 Supplemental SSE3 SSE4.1 Streaming SIMD Extensions 4.1 SSE4.2 Streaming SIMD Extensions 4.2 AVX Advanced Vector Extensions AVX2 Advanced Vector Extensions 2 AVX-512 Advanced Vector 512-bit (2 Units) AVX512F AVX-512 Foundation AVX512CD AVX-512 Conflict Detection AVX512BW AVX-512 Byte and Word AVX512DQ AVX-512 Doubleword and Quadword Instructions AVX512VL AVX-512 Vector Length ABM Advanced Bit Manipulation BMI1 Bit Manipulation Instruction Set 1 BMI2 Bit Manipulation Instruction Set 2 FMA3 3-Operand Fused-Multiply-Add AES AES Encryption Instructions RdRand Hardware RNG ADX Multi-Precision Add-Carry CLMUL Carry-less Multiplication Extension F16C 16-bit Floating Point Conversion x86-16 16-bit x86 x86-32 32-bit x86 x86-64 64-bit x86 Real Real Mode Protected Protected Mode SMM System Management Mode FPU Integrated x87 FPU NX No-eXecute HT Hyper-Threading TBT 2.0 Turbo Boost Technology 2.0 EIST Enhanced SpeedStep Technology SST Speed Shift Technology TXT Trusted Execution Technology (SMX) vPro Intel vPro VT-x VT-x (Virtualization) VT-d VT-d (I/O MMU virtualization) EPT Extended Page Tables (SLAT) TSX Transactional Synchronization Extensions MPX Memory Protection Extensions Secure Key Secure Key Technology SMEP OS Guard Technology VMD Volume Management Device IPT Identity Protection Technology

Frequencies

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

Mode	Base	Turbo Frequency/Active Cores
		1	2	3	4	5	6	7	8	9	10
Normal	3,000 MHz	4,500 MHz	4,500 MHz	4,300 MHz	4,300 MHz	4,100 MHz	4,100 MHz	4,100 MHz	4,100 MHz	3,800 MHz	3,800 MHz
AVX2		4,000 MHz	4,000 MHz	3,800 MHz	3,800 MHz	3,700 MHz	3,700 MHz	3,700 MHz	3,700 MHz	3,400 MHz	3,400 MHz
AVX512		4,000 MHz	4,000 MHz	3,800 MHz	3,800 MHz	3,200 MHz	3,200 MHz	3,200 MHz	3,200 MHz	3,000 MHz	3,000 MHz