Edit Values | |
NNP-T 1400 | |
![]() | |
NPU with 4 HBM2 stacks | |
General Info | |
Designer | Intel |
Manufacturer | TSMC |
Model Number | NNP-T 1400 |
Market | Server |
Introduction | November 12, 2019 (announced) November 12, 2019 (launched) |
Shop | Amazon |
General Specs | |
Family | NNP |
Series | NNP-T |
Frequency | 1,100 MHz |
Microarchitecture | |
Microarchitecture | Spring Crest |
Process | 16 nm |
Transistors | 27,000,000,000 |
Technology | CMOS |
Die | 680 mm² |
Cores | 24 |
Max Memory | 32 GiB |
Multiprocessing | |
Interconnect | InterChip Link |
Interconnect Links | 16 |
Interconnect Rate | 28 GT/s |
Electrical | |
Power dissipation | 175 W |
Packaging | |
Package | FCBGA-3325 (FCBGA) |
Dimension | 60 mm × 60 mm |
Contacts | 3325 |
![]() |
NNP-T 1400 is a neural processor designed by Intel Nervana and introduced in late 2019. Fabricated on TSMC 16 nm process based on the Spring Crest microarchitecture, the NNP-T 1400 has the full 24 TPCs enabled along with 60 MiB of scratchpad memory and operates at up to 1.1 GHz. This chip comes in an OAM accelerator card form factor and incorporates 32 GiB of HBM2 memory. This NPU exposes 16 inter-chip links for scale-out capabilities.
![](/w/images/thumb/8/87/spring_crest_mezzanine_card_%28front%29.png/300px-spring_crest_mezzanine_card_%28front%29.png)
Peak Performance
The NNP-T 1400 comes in an OCP OAM mezzanine card which enables support for various topologies including ring, hybrid cube mesh, and fully connected.
Cache
- Main article: Spring Crest § Cache
- 55 MiB of tightly-coupled scratchpad memory
- 22 x 2.5 MiB/core
Memory controller
![]() |
Integrated Memory Controller
|
|||||||||||
|
Interconnect Topology
The NNP-T 1300 comes in a dual-slot standard PCIe 4.0 card which enables support for only the ring topology. Chips are interconnected using the 16 available inter-chip links.
Product Brief
full page name | nervana/nnp/nnp-t 1400 + |
instance of | microprocessor + |
ldate | 1900 + |