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Mongoose 4 µarch
General Info
Arch Type	CPU
Designer	Samsung
Manufacturer	Samsung
Introduction	2019
Process	8 nm
Core Configs	4
Pipeline
Type	Superscalar, Superpipeline
OoOE	Yes
Speculative	Yes
Reg Renaming	Yes
Stages	16
Decode	6-way
Instructions
ISA	ARMv8.2
Cache
L1I Cache	64 KiB/core 4-way set associative
L1D Cache	64 KiB/core 8-way set associative
L2 Cache	512 KiB/core 8-way set associative
L3 Cache	4 MiB/cluster 16-way set associative
Succession
M3 M5

Exynos Mongoose 4 (M4) is the successor to the Mongoose 3, an 8 nm ARM microarchitecture designed by Samsung for their consumer electronics.

Process Technology

The M4 is fabricated on Samsung's 8 nm process (8LPP).

Compiler support

Compiler	Arch-Specific	Arch-Favorable
GCC	-mcpu=exynos-m4	-mtune=exynos-m4
LLVM	-mcpu=exynos-m4	-mtune=exynos-m4

Architecture

The M4 is an incremental microarchitecture that brought a die shrink and minor enhancements.

Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.

Key changes from M3

• 8 nm process (from 10 nm)
• ARMv8.2 (from ARMv8)
  • Support for full FP16 scalar extension
  • Suppot for integer dot product extension
• Front end
  • Larger instruction queue (48 entries, up from 40)
• Back end
  • LSU executiion units reorganized
  • Floating-point execution units reorganized

This list is incomplete; you can help by expanding it.

Block Diagram

Individual Core

Memory Hierarchy

This section is empty; you can help add the missing info by editing this page.

Core

The core of the M4 is largely the same as M3. A number of buffers have been enlarged and some of the execution units have been reorganized.

Execution engine

Floating-point cluster

The execution units on the M4 have been reorganized. In total, three new units were also added - a second FP square root unit, a second vector multiplication unit, and a new horizontal vector arithmetic unit.

Floating-point pipe changes.

Memory subsystem

A minor enhancement was made to the M4 memory subsystem. In the M3, there were three AGUs - two dedicated Load AGUs and a single dedicated Store AUG. In the M4, Samsung changed one of the dedicated Load AGUs into a generic AGU capable of handling both loads and stores. In other words, the M4 can now schedule both load and store µOPs on two ports.

All M3 Processors

	List of M4-based Processors
	Main processor					Integrated Graphics
Model	Family	Launched	Arch	Cores	Frequency	GPU	Frequency
Count: 0

Bibliography

• LLVM: lib/Target/AArch64/AArch64SchedExynosM4.td