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A4-9120C - AMD
Edit Values | |
A4-9120C | |
General Info | |
Designer | AMD |
Manufacturer | GlobalFoundries |
Model Number | A4-9120C |
Part Number | AM912CANN23AC |
Market | Mobile |
Introduction | January 6, 2019 (announced) January 6, 2019 (launched) |
Shop | Amazon |
General Specs | |
Family | A4 |
Series | A4-9000 |
Locked | Yes |
Frequency | 1,600 MHz |
Turbo Frequency | 2,400 MHz (1 core) |
Clock multiplier | 16 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Excavator |
Core Name | Bristol Ridge |
Process | 28 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 2 |
Threads | 2 |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
TDP | 6 W |
OP Temperature | 0° C – 90 °C |
Packaging | |
Unknown package "amd,socket_fp4" |
A4-9120C is a 64-bit dual-core ultra-low power x86 mobile microprocessor introduced by AMD in early 2019. This processor is based on AMD's Excavator microarchitecture and is fabricated on a 28 nm process. The A4-9120C operates at a base frequency of 1.6 GHz with a TDP of 6 W and a turbo frequency of 2.4 GHz. This APU supports single-channel DDR4-1866 memory and incorporates Radeon R4 series graphics operating at up to 600 MHz.
Cache
- Main article: Excavator § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
Expansion Options |
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Facts about "A4-9120C - AMD"
full page name | amd/a4/a4-9120c + |
instance of | microprocessor + |
ldate | 1900 + |