Interconnect Architectures

Concepts

Network On A Chip System Bus

General

AGP CAPI CCIX CCPI DMI (IBM) DMI (Intel) EISA Gen-Z Hydra HT IF ISA LIPINCON Micro Channel Multibus NVLink PCI PCIe PXI Q-Bus QPI S-100 SS-50 Unibus UPI VLB

Peripheral

1-Wire ACCESS.bus Centronics GPIB MIDI RS-232 RS-422 RS-423 UNI/O bus

Storage Devices

NVMe PATA SATA SATAe SSA SCSI

Audio Devices

I²S S/PDIF

Cavium Coherent Processor Interconnect (CCPI') is an interconnect architecture designed by Cavium for their microprocessors.

Overview

CCPI is a cache coherent interconnect architecture designed by Cavium for their various microprocessors. CCPI is used to support symmetric multiprocessing on the ThunderX and ThunderX2 families.

Data Rates

	CCPI	CCPI2
Signaling Rate	10 GT/s	25 GT/s
Lanes/Link	24	24
Rate/Link	30 GB/s 240 Gb/s	75 GB/s 600 Gb/s

This article is still a stub and needs your attention. You can help improve this article by editing this page and adding the missing information.