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Hi1610
General Info
Designer	HiSilicon, ARM Holdings
Manufacturer	TSMC
Model Number	Hi1610
Market	Server
Introduction	2015 (announced) 2015 (launched)
General Specs
Family	Hi16xx
Frequency	2,100 MHz
Microarchitecture
ISA	ARMv8 (ARM)
Microarchitecture	Cortex-A57
Core Name	Cortex-A57
Process	16 nm
Technology	CMOS
Word Size	64 bit
Cores	16
Threads	16
Max Memory	256 GiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)

Hi1610 is a hexadeca-core 64-bit ARM server microprocessor introduced by HiSilicon in late-2015. Fabricated by TSMC on a 16 nm process, this chip incorporates 16 Cortex-A57 cores operating at 2.1 GHz. The Hi1610 supports up to 256 GiB of quad-channel DDR4-1866 memory.

Cache

Main article: Cortex-A57 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 1.25 MiB 1,280 KiB 1,310,720 B L1I$ 768 MiB 786,432 KiB 805,306,368 B 16x48 KiB 8-way set associative   L1D$ 512 KiB 524,288 B 0.5 MiB 16x32 KiB 8-way set associative   L2$ 4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB     16x256 KiB 8-way set associative   L3$ 16 MiB 16,384 KiB 16,777,216 B 0.0156 GiB     16x1 MiB 16-way set associative

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR4-1866 Supports ECC Yes Max Mem 256 GiB Controllers 1 Channels 4 Width 64 bit Max Bandwidth 55.63 GiB/s 56,965.12 MiB/s 59.732 GB/s 59,732.258 MB/s 0.0543 TiB/s 0.0597 TB/s Bandwidth Single 13.91 GiB/s Double 27.81 GiB/s Quad 55.63 GiB/s

Expansions

[Edit/Modify Expansions Info]

	Expansion Options
PCIe Revision: 3.0 Max Lanes: 16 Configuration: 2x8