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ThunderX2 - Cavium
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Revision as of 22:13, 24 June 2018 by David (talk | contribs) (Models)

ThunderX2
ThunderX2 logo.png
ThunderX2
Developer Cavium
Manufacturer TSMC
Type Microprocessors
Introduction May 30, 2016 (announced)
May 7, 2018 (launch)
ISA ARMv8
µarch ThunderX2, Vulcan
Word size 64 bit
8 octets
16 nibbles
Process 14 nm
0.014 μm
1.4e-5 mm
, 16 nm
0.016 μm
1.6e-5 mm
Technology CMOS
Clock 2,500 MHz-1,600 MHz
Succession
ThunderX

ThunderX2 is a family of 64-bit multi-core ARM server microprocessors introduced by Cavium in early 2018 succeeding the original ThunderX line.

Overview

The ThunderX2 was designed to succeed the original ThunderX family. Cavium first announced the ThunderX2 back in May 30 2016 with models based on their own second-generation microarchitecture with models up to 54 cores. Cavium eventually scrapped their own design and in late 2016 they acquired the Vulcan design from Broadcom which has designed a server microprocessor but has given up on the project for reasons not well understood. In early 2018, Cavium announced that their ThunderX2 processors (now based on Vulcan) have reached general availability.

Models

Vulcan

The first parts of the ThunderX2 family that made it to general availability are based on the Vulcan microarchitecture. Those parts are different from Cavium's original ThunderX2 design which started sampling in 2016. Originally designed by Broadcom, those parts have much higher performance and a slightly different set of features. All parts have the following features in common.

  • Mem: Up to 2 TiB of quad/hexa/octa- channel DDR4 2666 MT/s memory
    • Up to 4 TiB in dual-socket configuration
  • ISA: ARMv8, 128-bit SVE
  • I/O: x48, x56 PCIe Gen 3 Lanes

See also

Facts about "ThunderX2 - Cavium"
designerCavium +
first announcedMay 30, 2016 +
first launchedMay 7, 2018 +
full page namecavium/thunderx2 +
instance ofmicroprocessor family +
instruction set architectureARMv8 +
main designerCavium +
manufacturerTSMC +
microarchitectureThunderX2 + and Vulcan +
nameThunderX2 +
process14 nm (0.014 μm, 1.4e-5 mm) + and 16 nm (0.016 μm, 1.6e-5 mm) +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +