From WikiChip
Isaiah - Microarchitectures - VIA Technologies
< via technologies
Revision as of 19:11, 15 January 2018 by At32Hz (talk | contribs)
(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)

Edit Values
Isaiah µarch
General Info
Arch TypeCPU
DesignerVIA Technologies
ManufacturerFujitsu, TSMC
Process65 nm, 40 nm
Core Configs2, 4
Instructions
ISAx86-64
Succession

Isaiah is the successor to Esther, an x86 microarchitecture designed by VIA Technologies for low power devices.

Brands

Family
via quadcore logo.png QuadCore

Process Technology

Isaiah was originally fabricated on Fujitsu's 65 nm process and later undergone a process shrink to TSMC's 40 nm process.

Architecture

Key changes from Esther

  • 65 nm (from 90 nm)

This list is incomplete; you can help by expanding it.

Retrieved from "https://en.wikichip.org/w/index.php?title=via_technologies/microarchitectures/isaiah&oldid=72579"
Facts about "Isaiah - Microarchitectures - VIA Technologies"
RDF feed
codenameIsaiah +
core count2 + and 4 +
designerVIA Technologies +
full page namevia technologies/microarchitectures/isaiah +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerFujitsu + and TSMC +
microarchitecture typeCPU +
nameIsaiah +
process65 nm (0.065 μm, 6.5e-5 mm) + and 40 nm (0.04 μm, 4.0e-5 mm) +