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K3V2E
General Info
Designer	HiSilicon, ARM Holdings
Manufacturer	TSMC
Model Number	K3V2E
Part Number	Hi3620
Market	Mobile
Introduction	2013 (announced) 2013 (launched)
General Specs
Family	K3
Frequency	1,500 MHz
Microarchitecture
ISA	ARMv7 (ARM)
Microarchitecture	Cortex-A9
Core Name	Cortex-A9
Process	40 nm
Transistors	600,000,000
Technology	CMOS
Word Size	32 bit
Cores	4
Threads	4
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Packaging
Package TFBGA-576 (BGA) Dimension 11.90 mm x 11.90 mm Pitch 0.5 mm Pins 576

K3V2E is a 32-bit quad-core mobile ARM microprocessor introduced by HiSilicon in 2013. This chip, which is fabricated on a 40 nm process, incorporates four Cortex-A9 cores operating at 1.5 GHz. The K3V2 integrated Vivante's GC4000 (16 cores) IGP and supports up to 2 channels of LPDDR2-900 memory. The K3V2E is an enhanced version of the K3V2, although the exact changes are not well-documented.

Cache

Main article: Cortex-A9 § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 256 KiB 262,144 B 0.25 MiB L1I$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB 4-way set associative   L1D$ 128 KiB 131,072 B 0.125 MiB 4x32 KiB 4-way set associative   L2$ 1 MiB 1,024 KiB 1,048,576 B 9.765625e-4 GiB     1x1 MiB 8-way set associative

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type LPDDR2-900 Supports ECC No Controllers 1 Channels 2 Width 32 bit Max Bandwidth 6.71 GiB/s 6,871.04 MiB/s 7.205 GB/s 7,204.808 MB/s 0.00655 TiB/s 0.0072 TB/s Bandwidth Single 3.35 GiB/s Double 6.71 GiB/s

Graphics

[Edit/Modify IGP Info]

	Integrated Graphics Information
	GPU GC4000 Designer Vivante Execution Units 16 Max Displays 1 Frequency 480 MHz 0.48 GHz 480,000 KHz Output DSI Max Resolution DSI 1920x1200 Standards DirectX 11 OpenGL 3.0 OpenCL 1.2 OpenGL ES 3.1 OpenVG 1.1

Expansions

• 4x high-speed UART interfaces
• 2x SPI
• 2x I2C + 2x I2C for camera
• USB 2.0 On-The-Go (HS OTG) PHY
• USB 1.1
• 2x MMC/SD/SDIO interface
• 22x GPIOs
• 10 Timers

Block Diagram

Utilizing devices

• Huawei HN3-U01
• Huawei Ascend P6 (P6-C00)
• Ascend W2 (W2‐T00)
• Huawei Honor 3

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