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Xeon Bronze 3104 - Intel
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Xeon Bronze 3104 | |
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General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 3104 |
Part Number | BX806733104, CD8067303562000 |
S-Spec | SR3GM QN0D (QS) |
Market | Server, Workstation |
Introduction | July 11, 2017 (announced) July 11, 2017 (launched) |
Release Price | $213.00 |
Shop | Amazon |
General Specs | |
Family | Xeon Bronze |
Series | 3000 |
Locked | Yes |
Frequency | 1,700 MHz |
Clock multiplier | 17 |
CPUID | 0x50654 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Skylake (server) |
Platform | Purley |
Chipset | Lewisburg |
Core Name | Skylake SP |
Core Family | 6 |
Core Stepping | U0 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 6 |
Threads | 6 |
Max Memory | 768 GiB |
Multiprocessing | |
Max SMP | 2-Way (Multiprocessor) |
Electrical | |
TDP | 85 W |
Tcase | 0 °C – 78 °C |
TDTS | 0 °C – 89 °C |
Packaging | |
Template:packages/intel/fclga-3647 |
Xeon Bronze 3104 is a 64-bit hexa-core x86 dual-socket entry-level server and workstation microprocessor introduced by Intel in mid-2017. The Bronze 3104, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm process sports 1 AVX-512 FMA unit as well as two Ultra Path Interconnect links. This microprocessor, which operates at 1.7 GHz with a TDP of 85 W, supports up 768 GiB of hexa-channel DDR4-2133 ECC memory.
Cache
- Main article: Skylake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Features
[Edit/Modify Supported Features]
Frequencies
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||
---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | ||
Normal | 1,700 MHz | 1,700 MHz | 1,700 MHz | 1,700 MHz | 1,700 MHz | 1,700 MHz | 1,700 MHz |
AVX2 | 1,300 MHz | 1,300 MHz | 1,300 MHz | 1,300 MHz | 1,300 MHz | 1,300 MHz | 1,300 MHz |
AVX512 | 800 MHz | 800 MHz | 800 MHz | 800 MHz | 800 MHz | 800 MHz | 800 MHz |
Facts about "Xeon Bronze 3104 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Bronze 3104 - Intel#io + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables + and Transactional Synchronization Extensions + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has second level address translation support | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
l1$ size | 384 KiB (393,216 B, 0.375 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 192 KiB (196,608 B, 0.188 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 192 KiB (196,608 B, 0.188 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 8.25 MiB (8,448 KiB, 8,650,752 B, 0.00806 GiB) + |
max memory bandwidth | 95.37 GiB/s (97,658.88 MiB/s, 102.403 GB/s, 102,402.758 MB/s, 0.0931 TiB/s, 0.102 TB/s) + |
max memory channels | 6 + |
max pcie lanes | 48 + |
supported memory type | DDR4-2133 + |