Template:mpu Xeon Silver 4116T is a 64-bit dodeca-core x86 dual-socket mid-range performance server microprocessor introduced by Intel in mid-2017. The Silver 4116T, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm process, sports 1 AVX-512 FMA unit as well as two Ultra Path Interconnect links. This microprocessor, which operates at 2.1 GHz with a TDP of 85 W and a turbo boost frequency of up to 3 GHz, supports up 768 GiB of hexa-channel DDR4-2400 ECC memory.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 768 KiB 786,432 B 0.75 MiB L1I$ 384 KiB 393,216 B 0.375 MiB 12x32 KiB 8-way set associative   L1D$ 384 KiB 393,216 B 0.375 MiB 12x32 KiB 8-way set associative write-back L2$ 12 MiB 12,288 KiB 12,582,912 B 0.0117 GiB     12x1 MiB 16-way set associative write-back L3$ 16.5 MiB 16,896 KiB 17,301,504 B 0.0161 GiB     12x1.375 MiB 11-way set associative write-back

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR4-2400 Supports ECC Yes Max Mem 768 GiB Controllers 2 Channels 6 Max Bandwidth 107.3 GiB/s 109,875.2 MiB/s 115.212 GB/s 115,212.498 MB/s 0.105 TiB/s 0.115 TB/s Bandwidth Single 17.88 GiB/s Double 35.76 GiB/s Quad 71.53 GiB/s Hexa 107.3 GiB/s