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Difference between revisions of "intel/microarchitectures/rocket lake"
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=== CPUID ===
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{| class="wikitable tc1 tc2 tc3 tc4 tc5"
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! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model !! Stepping
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| rowspan="2" | {{intel|Rocket Lake S|S|l=core}} || 0 || 0x6 || 0xA || 0x7 || 0x0-0x1
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| colspan="5" | Family 6 Model 167 Stepping 0-1<br>Stepping: A0=0, B0=1
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== Architecture ==
 
== Architecture ==

Revision as of 14:21, 25 June 2021

Edit Values
Rocket Lake µarch
General Info
Arch TypeAPU
DesignerIntel
ManufacturerIntel
Process14 nm
Core Configs4, 6, 8
Pipeline
TypeSuperscalar, Superpipeline
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages14-19
Decode5-way
Instructions
ISAx86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX
Cache
L1I Cache48 KiB/core
8-way set associative
L1D Cache32 KiB/core
8-way set associative
L2 Cache512 KiB/core
4-way set associative
L3 Cache2 MiB/core
Up to 16-way set associative
L4 Cache128 MiB/package
on Iris Pro GPUs only
Cores
Core NamesCypress Cove
Succession
Contemporary
Tiger Lake

Rocket Lake (RKL) is a planned microarchitecture designed by Intel as a successor to Comet Lake for desktops and high-performance mobile devices.


Codenames

Core Description Graphics Target
Rocket Lake S Mainstream performance GT2 Desktop performance to value, AiOs, and minis
Rocket Lake U Ultra-low power GT2 Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room

Brands

Intel is expected to release Rocket Lake under 3 main brand families:

Logo Family General Description Differentiating Features
Cores HT AVX AVX2 TBT ECC
core i3 logo (2015).png Core i3 Low-end Performance
core i5 logo (2015).png Core i5 Mid-range Performance
core i7 logo (2015).png Core i7 High-end Performance

Release Dates

Rocket Lake is expected to be released in Q1 2021.

Compatibility

New text document.svg This section is empty; you can help add the missing info by editing this page.

Rocket Lake will feature the same LGA1200 socket as Comet Lake. Rocket Lake is backwards compatible with Comet Lake. Rocket Lake will have new motherboards and a new 500 series chipset. Rocket Lake will not be compatible with Alder Lake.

Compiler support

Compiler Arch-Specific Arch-Favorable
ICC -march=? -mtune=?
GCC -march=? -mtune=?
LLVM -march=? -mtune=?
Visual Studio /arch:AVX2 /?

CPUID

Further information: Intel CPUIDs
Core Extended
Family 		Family Extended
Model 		Model Stepping
S 0 0x6 0xA 0x7 0x0-0x1
Family 6 Model 167 Stepping 0-1
Stepping: A0=0, B0=1

Architecture

Key changes from Comet Lake

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.
  • Display
  • I/O
    • PCIe 4.0 (from 3.0)
  • Memory
    • Faster memory for mainstream desktops (i.e., Rocket Lake S) DDR4-3200 (from DDR4-2933)
  • Packaging

See also

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/rocket_lake&oldid=99052"
Facts about "Rocket Lake - Microarchitectures - Intel"
RDF feed
codenameRocket Lake +
core count4 +, 6 + and 8 +
designerIntel +
full page nameintel/microarchitectures/rocket lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
nameRocket Lake +
pipeline stages (max)19 +
pipeline stages (min)14 +
process14 nm (0.014 μm, 1.4e-5 mm) +