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Difference between revisions of "intel/microarchitectures/alder lake"
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(https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg2242174.html →Hybrid Core/Atom Processors: #define INTEL_FAM6_ALDERLAKE 0x97) |
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{{future information}} | {{future information}} | ||
| + | == Process Technology== | ||
| + | |||
| + | == History == | ||
| + | |||
| + | == Architecture == | ||
| + | |||
| + | |||
| + | === Key changes from {{\\|Ice Lake}}=== | ||
| + | * Core | ||
| + | ** Hybrid Core(big core) & Atom(small core) microarchitecture | ||
Revision as of 05:09, 21 July 2020
| Edit Values | |
| Alder Lake µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2021 |
| Process | 10 nm |
| Instructions | |
| ISA | x86-64 |
| Succession | |
Alder Lake (ADL) is Intel's successor to Tiger Lake, a 10 nm microarchitecture for mainstream workstations, desktops, and mobile devices.
Process Technology
History
Architecture
Key changes from Ice Lake
- Core
- Hybrid Core(big core) & Atom(small core) microarchitecture
Facts about "Alder Lake - Microarchitectures - Intel"
| codename | Alder Lake + |
| designer | Intel + |
| first launched | 2021 + |
| full page name | intel/microarchitectures/alder lake + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Alder Lake + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |