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Difference between revisions of "intel/microarchitectures/willow cove"
(Added ram speeds, cache increase, interconnect changes, max core configuration, next gen Xe graphics) |
(Tiger lake) |
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|manufacturer=Intel | |manufacturer=Intel | ||
|introduction=2020 | |introduction=2020 | ||
| − | |process=10 nm | + | |process=10 nm++ |
|isa=x86-64 | |isa=x86-64 | ||
|predecessor=Sunny Cove | |predecessor=Sunny Cove | ||
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|successor link=intel/microarchitectures/golden cove | |successor link=intel/microarchitectures/golden cove | ||
}} | }} | ||
| − | '''Willow Cove''' is the successor to {{\\|Sunny Cove}}, a high-performance [[10 nm]] [[x86]] core microarchitecture designed by [[Intel]] for an array of server and client products, including {{\\|Tiger Lake}}. | + | '''Willow Cove''' is the successor to {{\\|Sunny Cove}}, a high-performance [[10 nm+]] [[x86]] core microarchitecture designed by [[Intel]] for an array of server and client products, including {{\\|Tiger Lake}}. |
== History == | == History == | ||
| Line 22: | Line 22: | ||
Willow Cove is designed to take advantage of Intel's [[10 nm process]]. | Willow Cove is designed to take advantage of Intel's [[10 nm process]]. | ||
| − | == Architecture == | + | == Architecture & General Changes == |
=== Key changes from {{\\|Sunny Cove}}=== | === Key changes from {{\\|Sunny Cove}}=== | ||
| + | *10nm+ | ||
* New cache subsystem | * New cache subsystem | ||
* Security features | * Security features | ||
| Line 34: | Line 35: | ||
*Up to 8 core 16 threads (Tiger Lake H series) | *Up to 8 core 16 threads (Tiger Lake H series) | ||
{{expand list}} | {{expand list}} | ||
| + | |||
| + | |||
| + | ==May the best architecture win! Zen3 VS Tiger Lake 🐯== | ||
==== New instructions ==== | ==== New instructions ==== | ||
Revision as of 09:29, 11 June 2020
| Edit Values | |
| Willow Cove µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2020 |
| Process | 10 nm++ |
| Instructions | |
| ISA | x86-64 |
| Succession | |
Willow Cove is the successor to Sunny Cove, a high-performance 10 nm+ x86 core microarchitecture designed by Intel for an array of server and client products, including Tiger Lake.
Contents
History
Willow Cove was originally unveiled by Intel at their 2018 architecture day. Willow Cove is intended to succeed Sunny Cove in the 2020 timeframe.
Process Technology
Willow Cove is designed to take advantage of Intel's 10 nm process.
Architecture & General Changes
Key changes from Sunny Cove
- 10nm+
- New cache subsystem
- Security features
- 125% increase in L2 cache per core (1.25Mb up from 0.5 Mb)
- 50% increase in L3 cache per core (3Mb up from 2Mb)
- Increased IPC compared to sunny cove
- Intel Xe graphics (up to 96 execution units compared to 64 execution units in ice lake)
- Tiger lake U & Y series offer up to LPDDR4X 4266Mhz
- Next generation PCIe 4.0
- Up to 8 core 16 threads (Tiger Lake H series)
This list is incomplete; you can help by expanding it.
May the best architecture win! Zen3 VS Tiger Lake 🐯
New instructions
Willow Cove introduced a number of new instructions:
- Control-flow Enforcement Technology (CET) enhancements
-
MOVDIR- Direct stores - Additional AVX-512 extensions:
-
AVX512_VP2INTERSECT- AVX-512 Vector Intersection Instructions
-
Only on server parts (Sapphire Rapids):
-
ENQCMD- Enqueue Stores
Bibliography
- Intel Architecture Day 2018, December 11, 2018
Facts about "Willow Cove - Microarchitectures - Intel"
| codename | Willow Cove + |
| designer | Intel + |
| first launched | 2020 + |
| full page name | intel/microarchitectures/willow cove + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Willow Cove + |