Difference between revisions of "intel/xeon gold/6242r"

	Edit Values
	Xeon Gold 6242R
	General Info
Designer	Intel
Manufacturer	Intel
Model Number	6242R
Market	Server
Introduction	February 24, 2020 (announced); February 24, 2020 (launched)
Release Price	$2,529.00 (tray)
Shop	Amazon
	General Specs
Family	Xeon Gold
Series	6200
Locked	Yes
Frequency	3,100 MHz
Turbo Frequency	4,100 MHz (1 core)
Bus type	DMI 3.0
Bus rate	4 × 8 GT/s
Clock multiplier	31
	Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Cascade Lake
Platform	Purley
Chipset	Lewisburg
Core Name	Cascade Lake R
Core Family	6
Core Model	85
Process	14 nm
Technology	CMOS
Word Size	64 bit
Cores	20
Threads	40
Max Memory	1 TiB
	Multiprocessing
Max SMP	2-Way (Multiprocessor)
Interconnect	UPI
Interconnect Links	2
Interconnect Rate	10.4 GT/s
	Electrical
TDP	205 W
Tcase	0 °C – 76 °C
	Packaging
Package	FCLGA-3647 (FCLGA)
Dimension	76.16 mm × 56.6 mm
Pitch	0.8585 mm × 0.9906 mm
Contacts	3647
Socket	Socket P, LGA-3647
	Succession
	Xeon Gold 6242

Revision as of 01:07, 28 February 2020

Xeon Gold 6242R is a 64-bit 20-core x86 high performance server microprocessor introduced by Intel in early 2020. The Gold 6242R is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 2-way multiprocessing, sports 2 AVX-512 FMA units as well as two Ultra Path Interconnect links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 3.1 GHz with a TDP of 205 W and features a turbo boost frequency of up to 4.1 GHz.

Cache

Main article: Skylake § Cache

The Xeon Gold 6242R features a larger non-default 35.75 MiB of L3, a size that would normally be found on a 26-core part.

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

1.25 MiB

1,280 KiB
1,310,720 B

L1I$	640 KiB 655,360 B 0.625 MiB	20x32 KiB	8-way set associative
L1D$	640 KiB 655,360 B 0.625 MiB	20x32 KiB	8-way set associative	write-back

L2$

20 MiB

20,480 KiB
20,971,520 B
0.0195 GiB

		20x1 MiB	16-way set associative	write-back

L3$

35.75 MiB

36,608 KiB
37,486,592 B
0.0349 GiB

		26x1.375 MiB	11-way set associative	write-back

@@ Line 45: / Line 45: @@
 }}
 '''Xeon Gold 6242R''' is a {{arch|64}} [[20-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2020]]. The Gold 6242R is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 2-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as two {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 3.1 GHz with a TDP of 205 W and features a {{intel|turbo boost}} frequency of up to 4.1 GHz.
+== Cache ==
+{{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}}
+The Xeon Gold 6242R features a larger non-default 35.75 MiB of [[L3]], a size that would normally be found on a 26-core part.
+{{cache size
+|l1 cache=1.25 MiB
+|l1i cache=640 KiB
+|l1i break=20x32 KiB
+|l1i desc=8-way set associative
+|l1d cache=640 KiB
+|l1d break=20x32 KiB
+|l1d desc=8-way set associative
+|l1d policy=write-back
+|l2 cache=20 MiB
+|l2 break=20x1 MiB
+|l2 desc=16-way set associative
+|l2 policy=write-back
+|l3 cache=35.75 MiB
+|l3 break=26x1.375 MiB
+|l3 desc=11-way set associative
+|l3 policy=write-back
+}}

base frequency	3,100 MHz (3.1 GHz, 3,100,000 kHz) +
bus links	4 +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus type	DMI 3.0 +
chipset	Lewisburg +
clock multiplier	31 +
core count	20 +
core family	6 +
core model	85 +
core name	Cascade Lake R +
designer	Intel +
family	Xeon Gold +
first announced	February 24, 2020 +
first launched	February 24, 2020 +
full page name	intel/xeon gold/6242r +
has locked clock multiplier	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	1,280 KiB (1,310,720 B, 1.25 MiB) +
l1d$ description	8-way set associative +
l1d$ size	640 KiB (655,360 B, 0.625 MiB) +
l1i$ description	8-way set associative +
l1i$ size	640 KiB (655,360 B, 0.625 MiB) +
l2$ description	16-way set associative +
l2$ size	20 MiB (20,480 KiB, 20,971,520 B, 0.0195 GiB) +
l3$ description	11-way set associative +
l3$ size	35.75 MiB (36,608 KiB, 37,486,592 B, 0.0349 GiB) +
ldate	February 24, 2020 +
main image	+
manufacturer	Intel +
market segment	Server +
max case temperature	349.15 K (76 °C, 168.8 °F, 628.47 °R) +
max cpu count	2 +
max memory	1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) +
microarchitecture	Cascade Lake +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
model number	6242R +
name	Xeon Gold 6242R +
package	FCLGA-3647 +
platform	Purley +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 2,529.00 (€ 2,276.10, £ 2,048.49, ¥ 261,321.57) +
release price (tray)	$ 2,529.00 (€ 2,276.10, £ 2,048.49, ¥ 261,321.57) +
series	6200 +
smp interconnect	UPI +
smp interconnect links	2 +
smp interconnect rate	10.4 GT/s +
smp max ways	2 +
socket	Socket P + and LGA-3647 +
tdp	205 W (205,000 mW, 0.275 hp, 0.205 kW) +
technology	CMOS +
thread count	40 +
turbo frequency (1 core)	4,100 MHz (4.1 GHz, 4,100,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +

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Revision as of 01:07, 28 February 2020

Cache