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Difference between revisions of "preferred networks/microarchitectures/mn-core"
(mn-core) |
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Line 1: | Line 1: | ||
{{pfn title|MN-Core}} | {{pfn title|MN-Core}} | ||
{{microarchitecture | {{microarchitecture | ||
+ | |atype=NPU | ||
|name=MN-Core | |name=MN-Core | ||
+ | |designer=Preferred Networks | ||
+ | |manufacturer=TSMC | ||
+ | |introduction=2020 | ||
+ | |process=12 nm | ||
+ | |processing elements=512 | ||
}} | }} | ||
'''MN-Core''' is a [[neural processor]] microarchitecture designed by [[Preferred Networks]] for its {{pfn|mn|own series of supercomputers}}. | '''MN-Core''' is a [[neural processor]] microarchitecture designed by [[Preferred Networks]] for its {{pfn|mn|own series of supercomputers}}. |
Latest revision as of 14:47, 27 November 2019
Edit Values | |
MN-Core µarch | |
General Info | |
Arch Type | NPU |
Designer | Preferred Networks |
Manufacturer | TSMC |
Introduction | 2020 |
Process | 12 nm |
PE Configs | 512 |
MN-Core is a neural processor microarchitecture designed by Preferred Networks for its own series of supercomputers.
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