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Difference between revisions of "amd/ryzen 9/3900x"
< amd‎ | ryzen 9

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|l3 break=4x16 MiB
 
|l3 break=4x16 MiB
 
|l3 desc=16-way set associative
 
|l3 desc=16-way set associative
 +
}}
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 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR4-3200
 +
|max mem=64 GiB
 +
|channels=2
 +
|max bandwidth=47.68 GiB/s
 +
|bandwidth schan=23.84 GiB/s
 +
|bandwidth dchan=47.68 GiB/s
 
}}
 
}}

Revision as of 13:00, 27 May 2019

Edit Values
Ryzen 9 3900X
General Info
DesignerAMD
ManufacturerTSMC
Model Number3900X
MarketDesktop
IntroductionMay 27, 2019 (announced)
July 7, 2019 (launched)
Release Price$499
ShopAmazon
General Specs
FamilyRyzen 9
Series3000
LockedNo
Frequency3,800 MHz
Turbo Frequency4,600 MHz
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureZen 2
Core NameMatisse
Process7 nm
TechnologyCMOS
Word Size64 bit
Cores12
Threads24
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP105 W
Packaging
Template:packages/amd/socket am4

Ryzen 9 3900X is a 64-bit dodeca-core high-end performance x86 desktop microprocessor introduced by AMD in mid-2019. Fabricated on TSMC's 7 nm process based on the Zen 2 microarchitecture, this processor operates at 3.8 GHz with a TDP of 105 W and a Boost frequency of up to 4.6 GHz.

Cache

Main article: Zen 2 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1.125 MiB
1,152 KiB
1,179,648 B
L1I$768 KiB
786,432 B
0.75 MiB
12x64 KiB4-way set associative 
L1D$384 KiB
393,216 B
0.375 MiB
12x32 KiB8-way set associativewrite-back
L2$6 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
  12x512 KiB8-way set associativewrite-back
L3$64 MiB
65,536 KiB
67,108,864 B
0.0625 GiB
  4x16 MiB16-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-3200
Max Mem64 GiB
Channels2
Max Bandwidth47.68 GiB/s
48,824.32 MiB/s
51.196 GB/s
51,196.01 MB/s
0.0466 TiB/s
0.0512 TB/s
Bandwidth
Single 23.84 GiB/s
Double 47.68 GiB/s
Retrieved from "https://en.wikichip.org/w/index.php?title=amd/ryzen_9/3900x&oldid=91255"
Facts about "Ryzen 9 3900X - AMD"
RDF feed
base frequency3,800 MHz (3.8 GHz, 3,800,000 kHz) +
core count12 +
core nameMatisse +
designerAMD +
familyRyzen 9 +
first announcedMay 27, 2019 +
first launchedJuly 7, 2019 +
full page nameamd/ryzen 9/3900x +
has ecc memory supportfalse +
has locked clock multiplierfalse +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size1,152 KiB (1,179,648 B, 1.125 MiB) +
l1d$ description8-way set associative +
l1d$ size384 KiB (393,216 B, 0.375 MiB) +
l1i$ description4-way set associative +
l1i$ size768 KiB (786,432 B, 0.75 MiB) +
l2$ description8-way set associative +
l2$ size6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) +
l3$ description16-way set associative +
l3$ size64 MiB (65,536 KiB, 67,108,864 B, 0.0625 GiB) +
ldate3000 +
manufacturerTSMC +
market segmentDesktop +
max cpu count1 +
max memory bandwidth47.68 GiB/s (48,824.32 MiB/s, 51.196 GB/s, 51,196.01 MB/s, 0.0466 TiB/s, 0.0512 TB/s) +
max memory channels2 +
microarchitectureZen 2 +
model number3900X +
nameRyzen 9 3900X +
process7 nm (0.007 μm, 7.0e-6 mm) +
release price$ 499.00 (€ 449.10, £ 404.19, ¥ 51,561.67) +
series3000 +
smp max ways1 +
supported memory typeDDR4-3200 +
tdp105 W (105,000 mW, 0.141 hp, 0.105 kW) +
technologyCMOS +
thread count24 +
turbo frequency4,600 MHz (4.6 GHz, 4,600,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +